公开(公告)号：US20070007663A1

公开(公告)日：2007-01-11

申请号：US11371291

申请日：2006-03-07

申请人： Seung-Duk Baek ,  Sun-Won Kang

发明人： Seung-Duk Baek ,  Sun-Won Kang

IPC分类号： H01L23/48

CPC分类号： H01L23/3114 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/50 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/86 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/838 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An embodiment includes a dual interconnection form in which power/ground pads and signal pads of a semiconductor chip are electrically connected to a package substrate in different connection manners. First connection members that electrically connect the power/ground pads with the substrate have relatively large cross-sectional dimensions in comparison to its length, for example, solder bumps or gold bumps. Second connection members that electrically connect the signal pads with the substrate have relatively small cross-sectional dimensions in comparison its length, for example, conductive wires or beam leads. Such different ways of electrically connecting different kinds of pads with the substrate realize the most suitable electrical performance, effectively meeting the needs of high speed and low power consumption of the semiconductor devices.

摘要翻译： 一个实施例包括双重互连形式，其中半导体芯片的电源/接地焊盘和信号焊盘以不同的连接方式电连接到封装基板。 将电源/接地焊盘与基板电连接的第一连接构件与其长度（例如，焊料凸块或金凸块）相比具有相对较大的横截面尺寸。 将信号焊盘与衬底电连接的第二连接构件与其长度（例如，导线或束引线）相比具有相对小的横截面尺寸。 将不同类型的焊盘与衬底电连接的这种不同的方式实现了最适合的电气性能，有效地满足了半导体器件的高速度和低功耗的需要。

公开(公告)号：US08928154B2

公开(公告)日：2015-01-06

申请号：US13344803

申请日：2012-01-06

申请人： Sun-Won Kang ,  Young-Hee Song ,  Tae-Gyeong Chung ,  Nam-Seog Kim ,  Seung-Duk Baek

发明人： Sun-Won Kang ,  Young-Hee Song ,  Tae-Gyeong Chung ,  Nam-Seog Kim ,  Seung-Duk Baek

IPC分类号： H01L29/40 ,  H01L25/065 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L24/06 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/45099 ,  H01L2924/00

摘要： A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die.

公开(公告)号：US08174860B2

公开(公告)日：2012-05-08

申请号：US13042049

申请日：2011-03-07

申请人： Sun-Won Kang ,  Seung-Duk Baek

发明人： Sun-Won Kang ,  Seung-Duk Baek

IPC分类号： G11C5/06 ,  G11C5/00 ,  H01L23/02 ,  H01L23/48

CPC分类号： G11C5/063 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Provided are a semiconductor memory device and a method of driving the device which can improve a noise characteristic of a voltage signal supplied to a memory cell of the device. The semiconductor memory device includes a first semiconductor chip and one or more second semiconductor chips stacked on the first chip. The first chip includes an input/output circuit for sending/receiving a voltage signal, a data signal, and a control signal to/from an outside system. The one or more second semiconductor chips each include a memory cell region for storing data. The second semiconductor chips receive at least one signal through one or more signal paths that are formed outside the input/output circuit of the first chip.

摘要翻译： 提供一种半导体存储器件和驱动器件的方法，该器件可以改善提供给器件的存储单元的电压信号的噪声特性。 半导体存储器件包括第一半导体芯片和堆叠在第一芯片上的一个或多个第二半导体芯片。 第一芯片包括用于向/从外部系统发送/接收电压信号，数据信号和控制信号的输入/输出电路。 一个或多个第二半导体芯片各自包括用于存储数据的存储单元区域。 第二半导体芯片通过形成在第一芯片的输入/输出电路外部的一个或多个信号路径接收至少一个信号。

公开(公告)号：US20090166840A1

公开(公告)日：2009-07-02

申请号：US12342689

申请日：2008-12-23

申请人： Sun-Won KANG ,  Seung-Duk Baek

发明人： Sun-Won KANG ,  Seung-Duk Baek

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A wafer-level stack package includes semiconductor chips, first connection members, a second connection member, a substrate and an external connection terminal. The semiconductor chips have a power/ground pad and a signal pad. The first connection members are electrically connected to the power/ground pad and the signal pad of each of the semiconductor chips. The second connection member is electrically connected to at least one of the power/ground pads of each of the semiconductor chips, the power/ground pads being connected to the first connection members. The substrate supports the stacked semiconductor chips, the substrate including wirings that are electrically connected to the first connection members and the second connection member. The external connection terminal is provided on a surface of the substrate opposite to a surface where the semiconductor chips are stacked, wherein the external connection terminals are electrically connected to the wirings, respectively.

摘要翻译： 晶圆级堆叠封装包括半导体芯片，第一连接构件，第二连接构件，基板和外部连接端子。 半导体芯片具有电源/接地焊盘和信号焊盘。 第一连接构件电连接到电源/接地焊盘和每个半导体芯片的信号焊盘。 第二连接构件电连接到每个半导体芯片的功率/接地焊盘中的至少一个，电源/接地焊盘连接到第一连接构件。 基板支撑层叠的半导体芯片，基板包括电连接到第一连接构件和第二连接构件的布线。 外部连接端子设置在与半导体芯片堆叠的表面相对的表面上，其中外部连接端子分别电连接到布线。

公开(公告)号：US20090127717A1

公开(公告)日：2009-05-21

申请号：US12292196

申请日：2008-11-13

申请人： Sun-Won Kang ,  Young-Hee Song ,  Tae-Gyeong Chung ,  Nam-Seog Kim ,  Seung-Duk Baek

发明人： Sun-Won Kang ,  Young-Hee Song ,  Tae-Gyeong Chung ,  Nam-Seog Kim ,  Seung-Duk Baek

IPC分类号： H01L23/49

CPC分类号： H01L25/0657 ,  H01L24/06 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/45099 ,  H01L2924/00

摘要： A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die.

摘要翻译： 半导体模块可以包括在电路基板上具有第一裸片的电路基板和在第一裸片上的第二裸片。 第一裸片可以包括在第一裸片的第一周边部分上的至少一个第一数据输入/输出焊盘和第三外围部分上的至少一个第一控制/地址焊盘，第三外围部分与第一外围部分的第一外围部分分离 第一个死亡 第二管芯可以包括在第二外围部分上的至少一个第二数据输入/输出焊盘和第四外围部分上的至少一个第二控制/地址焊盘。 第二模具的第二周边部分在平面图中不与第一模具的第一周边部分重叠。 第二模具的第四周边部分与第一模具的第三周边部分的至少一部分重叠。

公开(公告)号：US20050269684A1

公开(公告)日：2005-12-08

申请号：US11137803

申请日：2005-05-26

申请人： Seung-Duk Baek ,  Dong-Hyeon Jang ,  Jong-Joo Lee

发明人： Seung-Duk Baek ,  Dong-Hyeon Jang ,  Jong-Joo Lee

IPC分类号： H01L21/768 ,  H01L21/44 ,  H01L23/31 ,  H01L23/48 ,  H01L23/485 ,  H01L23/50 ,  H01L23/525

CPC分类号： H01L24/10 ,  H01L21/76802 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A semiconductor device package includes a substrate, first and second chip pads spaced apart over a surface of the substrate, and an insulating layer located over the surface of the substrate. The insulating layer includes a stepped upper surface defined by at least a lower reference potential line support surface portion, and an upper signal line support surface portion, where a thickness of the insulating layer at the lower reference potential line support surface portion is less than a thickness of the insulating layer at the upper signal line support surface portion. The package further includes a conductive reference potential line electrically connected to the first chip pad and located on the lower reference potential support surface portion of the insulating layer, a conductive signal line electrically connected to the second chip pad and located on the upper signal line support surface portion, and first and second external terminals electrically connected to the conductive reference potential line and the conductive signal line, respectively.

摘要翻译： 半导体器件封装包括衬底，在衬底的表面上间隔开的第一和第二芯片焊盘以及位于衬底表面上的绝缘层。 绝缘层包括由至少一个下参考电位线支撑表面部分限定的阶梯状上表面和上信号线支撑表面部分，其中下参考电位线支撑表面部分处的绝缘层的厚度小于 上部信号线支撑表面部分处的绝缘层的厚度。 所述封装还包括电连接到所述第一芯片焊盘并且位于所述绝缘层的下参考电位支撑表面部分上的导电参考电位线，电连接到所述第二芯片焊盘并位于所述上信号线支撑件上的导电信号线 表面部分以及分别电连接到导电参考电位线和导电信号线的第一和第二外部端子。

公开(公告)号：US07274097B2

公开(公告)日：2007-09-25

申请号：US11137803

申请日：2005-05-26

申请人： Seung-Duk Baek ,  Dong-Hyeon Jang ,  Jong-Joo Lee

发明人： Seung-Duk Baek ,  Dong-Hyeon Jang ,  Jong-Joo Lee

IPC分类号： H01L23/02 ,  H01L21/44

CPC分类号： H01L24/10 ,  H01L21/76802 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A semiconductor device package includes a substrate, first and second chip pads spaced apart over a surface of the substrate, and an insulating layer located over the surface of the substrate. The insulating layer includes a stepped upper surface defined by at least a lower reference potential line support surface portion, and an upper signal line support surface portion, where a thickness of the insulating layer at the lower reference potential line support surface portion is less than a thickness of the insulating layer at the upper signal line support surface portion. The package further includes a conductive reference potential line electrically connected to the first chip pad and located on the lower reference potential support surface portion of the insulating layer, a conductive signal line electrically connected to the second chip pad and located on the upper signal line support surface portion, and first and second external terminals electrically connected to the conductive reference potential line and the conductive signal line, respectively.

摘要翻译： 半导体器件封装包括衬底，在衬底的表面上间隔开的第一和第二芯片焊盘以及位于衬底表面上的绝缘层。 绝缘层包括由至少一个下参考电位线支撑表面部分限定的阶梯状上表面和上信号线支撑表面部分，其中下参考电位线支撑表面部分处的绝缘层的厚度小于 上部信号线支撑表面部分处的绝缘层的厚度。 所述封装还包括电连接到所述第一芯片焊盘并且位于所述绝缘层的下参考电位支撑表面部分上的导电参考电位线，电连接到所述第二芯片焊盘并位于所述上信号线支撑件上的导电信号线 表面部分以及分别电连接到导电参考电位线和导电信号线的第一和第二外部端子。

公开(公告)号：US08110922B2

公开(公告)日：2012-02-07

申请号：US12588231

申请日：2009-10-08

申请人： Hyun-Soo Chung ,  Seung-Duk Baek ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang

发明人： Hyun-Soo Chung ,  Seung-Duk Baek ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang

IPC分类号： H01L23/48

CPC分类号： H01L23/3114 ,  H01L24/10 ,  H01L24/13 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

摘要： A wafer level semiconductor module may include a module board and an IC chip set mounted on the module board. The IC chip set may include a plurality of IC chips having scribe lines areas between the adjacent IC chips. Each IC chip may have a semiconductor substrate having an active surface with a plurality of chip pads and a back surface. A passivation layer may be provided on the active surface of the semiconductor substrate of each IC chip and may having openings through which the chip pads may be exposed. Sealing portions may be formed in scribe line areas.

摘要翻译： 晶片级半导体模块可以包括安装在模块板上的模块板和IC芯片组。 IC芯片组可以包括在相邻IC芯片之间具有划线区域的多个IC芯片。 每个IC芯片可以具有具有多个芯片焊盘和后表面的有源表面的半导体衬底。 可以在每个IC芯片的半导体衬底的有源表面上提供钝化层，并且可以具有可以暴露芯片焊盘的开口。 密封部分可以形成在划线区域中。

公开(公告)号：US20090184411A1

公开(公告)日：2009-07-23

申请号：US12353501

申请日：2009-01-14

申请人： Hyun-Soo CHUNG ,  Jae-Shin Cho ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang ,  Seung-Duk Baek

发明人： Hyun-Soo CHUNG ,  Jae-Shin Cho ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang ,  Seung-Duk Baek

IPC分类号： H01L23/48

CPC分类号： H01L24/91 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00

摘要： Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure.

摘要翻译： 提供半导体封装和制造半导体封装的方法。 半导体封装可以包括衬底，其包括芯片焊盘，电连接到芯片焊盘并且包括开口的再分布线。 半导体封装还可以包括外部端子连接部分和设置在开口处并电连接到重新分配线路的外部端子连接焊盘。 本发明的总体构思可以解决包含在再分布线中的金的成分被阻止扩散到相邻的凸块焊盘中以形成空隙或不期望的金属间化合物的问题。 在片上芯片结构中，下部芯片的多个凸起连接到上部芯片以提高片上芯片结构的可靠性，分集性和功能性。

公开(公告)号：US20070246826A1

公开(公告)日：2007-10-25

申请号：US11585088

申请日：2006-10-24

申请人： Hyun-Soo Chung ,  Seung-Duk Baek ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang

发明人： Hyun-Soo Chung ,  Seung-Duk Baek ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang

IPC分类号： H01L23/48

CPC分类号： H01L23/3114 ,  H01L24/10 ,  H01L24/13 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

摘要： A wafer level semiconductor module may include a module board and an IC chip set mounted on the module board. The IC chip set may include a plurality of IC chips having scribe lines areas between the adjacent IC chips. Each IC chip may have a semiconductor substrate having an active surface with a plurality of chip pads and a back surface. A passivation layer may be provided on the active surface of the semiconductor substrate of each IC chip and may having openings through which the chip pads may be exposed. Sealing portions may be formed in scribe line areas.

摘要翻译： 晶片级半导体模块可以包括安装在模块板上的模块板和IC芯片组。 IC芯片组可以包括在相邻IC芯片之间具有划线区域的多个IC芯片。 每个IC芯片可以具有具有多个芯片焊盘和后表面的有源表面的半导体衬底。 可以在每个IC芯片的半导体衬底的有源表面上提供钝化层，并且可以具有可以暴露芯片焊盘的开口。 密封部分可以形成在划线区域中。