公开(公告)号：US09601500B2

公开(公告)日：2017-03-21

申请号：US14639063

申请日：2015-03-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Vipin Tiwari ,  Nhan Do ,  Xian Liu ,  Xiaozhou Qian ,  Ning Bai ,  Kai Man Yue

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC classification number: H01L27/11524 ,  H01L23/57 ,  H01L27/11226 ,  H01L27/11233 ,  H01L27/11253 ,  H01L27/11519 ,  H01L29/42328 ,  H01L29/788 ,  H01L29/7881

Abstract: A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.

公开(公告)号：US20160379941A1

公开(公告)日：2016-12-29

申请号：US15258069

申请日：2016-09-07

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Vipin Tiwari ,  Nhan Do ,  Xian Liu ,  Xiaozhou Qian ,  Ning Bai ,  Kai Man Yue

IPC: H01L23/00 ,  H01L29/423 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L27/11524 ,  H01L23/57 ,  H01L27/11226 ,  H01L27/11233 ,  H01L27/11253 ,  H01L27/11519 ,  H01L29/42328 ,  H01L29/788 ,  H01L29/7881

Abstract: A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.

公开(公告)号：US20160359024A1

公开(公告)日：2016-12-08

申请号：US15164796

申请日：2016-05-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  Vipin Tiwari

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/265 ,  H01L27/115 ,  H01L21/28

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L27/11529 ,  H01L29/66484 ,  H01L29/7885

Abstract: A method of forming a memory device on a semiconductor substrate having a memory region (with floating and control gates), a first logic region (with first logic gates) and a second logic region (with second logic gates). A first implantation forms the source regions adjacent the floating gates in the memory region, and the source and drain regions adjacent the first logic gates in the first logic region. A second implantation forms the source and drain regions adjacent the second logic gates in the second logic region. A third implantation forms the drain regions adjacent the control gates in the memory region, and enhances the source region in the memory region and the source/drain regions in the first logic region. A fourth implantation enhances the source/drain regions in the second logic region.

Abstract translation: 在具有存储区域（具有浮动和控制栅极）的第一逻辑区域（具有第一逻辑门）和第二逻辑区域（具有第二逻辑门）的半导体衬底上形成存储器件的方法。 第一注入形成与存储区域中的浮置栅极相邻的源极区域，以及与第一逻辑区域中的第一逻辑门极相邻的源区域和漏极区域。 第二注入形成与第二逻辑区域中的第二逻辑门相邻的源区和漏区。 第三注入形成与存储器区域中的控制栅极相邻的漏极区域，并且增强第一逻辑区域中的存储区域和源极/漏极区域中的源极区域。 第四次注入增强了第二逻辑区域中的源极/漏极区域。

公开(公告)号：US20140269061A1

公开(公告)日：2014-09-18

申请号：US13958415

申请日：2013-08-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen ,  Vipin Tiwari

IPC: G11C16/28 ,  G11C16/06

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C16/00 ,  G11C16/06 ,  G11C16/24 ,  G11C16/26 ,  G11C2207/063 ,  H01L27/11519

Abstract: Improved sensing circuits and improved bit line layouts for advanced nanometer flash memory devices are disclosed.

Abstract translation: 公开了用于高级纳米闪存器件的改进的感测电路和改进的位线布局。

公开(公告)号：US12057160B2

公开(公告)日：2024-08-06

申请号：US18123921

申请日：2023-03-20

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Farnood Merrikh Bayat ,  Xinjie Guo ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten

IPC: G11C11/00 ,  G06F3/06 ,  G06N3/04 ,  G06N3/045 ,  G06N3/063 ,  G11C11/54 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C29/38

CPC classification number: G11C11/54 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06N3/04 ,  G06N3/045 ,  G06N3/063 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G11C16/3436 ,  G11C29/38

Abstract: Numerous examples of summing circuits for a neural network are disclosed. In one example, a circuit for summing current received from a plurality of synapses in a neural network comprises a voltage source; a load coupled between the voltage source and an output node; a voltage clamp coupled to the output node for maintaining a voltage at the output node; and a plurality of synapses coupled between the output node and ground; wherein an output current flows through the output node, the output current equal to a sum of currents drawn by the plurality of synapses.

公开(公告)号：US12046290B2

公开(公告)日：2024-07-23

申请号：US17125459

申请日：2020-12-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G11C16/10 ,  G06N3/065 ,  G11C16/16

CPC classification number: G11C16/107 ,  G06N3/065 ,  G11C16/16

Abstract: Numerous embodiments of programming, verifying, and reading systems and methods for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Selected cells can be programmed and verified with extreme precision to hold one of N different values. During a read operation, the system determines which of the N different values is stored in a selected cell.

公开(公告)号：US11972795B2

公开(公告)日：2024-04-30

申请号：US18120360

申请日：2023-03-10

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Farnood Merrikh Bayat ,  Xinjie Guo ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten

IPC: G11C11/54 ,  G06F3/06 ,  G06N3/04 ,  G06N3/045 ,  G06N3/063 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C29/38

CPC classification number: G11C11/54 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06N3/04 ,  G06N3/045 ,  G06N3/063 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G11C16/3436 ,  G11C29/38

Abstract: Numerous examples are disclosed for verifying a weight programmed into a selected non-volatile memory cell in a neural memory. In one example, a circuit comprises a digital-to-analog converter to convert a target weight comprising digital bits into a target voltage, a current-to-voltage converter to convert an output current from the selected non-volatile memory cell during a verify operation into an output voltage, and a comparator to compare the output voltage to the target voltage during a verify operation.

公开(公告)号：US11790208B2

公开(公告)日：2023-10-17

申请号：US17238077

申请日：2021-04-22

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Farnood Merrikh Bayat ,  Xinjie Guo ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten

IPC: G06N3/04 ,  G11C11/54 ,  G06N3/063 ,  G11C16/34 ,  G11C29/38 ,  G06N3/045 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G06F3/06

CPC classification number: G06N3/04 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06N3/045 ,  G06N3/063 ,  G11C11/54 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G11C16/3436 ,  G11C29/38

Abstract: A number of circuits for use in an output block coupled to a non-volatile memory array in a neural network are disclosed. The embodiments include a circuit for converting an output current from a neuron in a neural network into an output voltage, a circuit for converting a voltage received on an input node into an output current, a circuit for summing current received from a plurality of neurons in a neural network, and a circuit for summing current received from a plurality of neurons in a neural network.

公开(公告)号：US11755899B2

公开(公告)日：2023-09-12

申请号：US16751202

申请日：2020-01-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G11C16/04 ,  G06N3/065 ,  G06F17/16 ,  G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  G11C16/14 ,  G06N3/044

CPC classification number: G06N3/065 ,  G06F17/16 ,  G06N3/044 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3459 ,  G11C2216/04

Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

公开(公告)号：US11682459B2

公开(公告)日：2023-06-20

申请号：US17082956

申请日：2020-10-28

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Stephen Trinh ,  Thuan Vu ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/14 ,  G06N3/065

CPC classification number: G11C16/10 ,  G06N3/065 ,  G11C11/5628 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/14 ,  G11C16/3459

Abstract: Two or more physical memory cells are grouped together to form a logical cell that stores one of N possible levels. Within each logical cell, the memory cells can be programmed using different mechanisms. For example, one or more of the memory cells in a logical cell can be programmed using a coarse programming mechanism, one or more of the memory cells can be programmed using a fine mechanism, and one or more of the memory cells can be programmed using a tuning mechanism. This achieves extreme programming accuracy and programming speed.