公开(公告)号：US20210104465A1

公开(公告)日：2021-04-08

申请号：US17125195

申请日：2020-12-17

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Jun-Chang Ding ,  Hong-Da Chang ,  Hsi-Chang Hsu

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/532 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: An electronic package, a packaging substrate, and methods for fabricating the same are disposed. The electronic package includes a circuit structure having a first side and a second side opposing the first side, an electronic component disposed on the first side of the circuit structure, an encapsulation layer formed on the first side of the circuit structure and encapsulating the electronic component, a metal structure disposed on the second side of the circuit structure, and a plurality of conductive elements disposed on the metal structure. The plurality of conductive elements are disposed on the metal structure, rather than disposed on the circuit structure directly. Therefore, the bonding between the conductive elements and the circuit structure is improved, to avoid the plurality of conductive elements from being peeled.

公开(公告)号：US20180068983A1

公开(公告)日：2018-03-08

申请号：US15494814

申请日：2017-04-24

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hong-Da Chang ,  Yih-Jenn Jiang

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L21/768 ,  H01L21/56 ,  H01L25/00 ,  H01L21/683

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/03 ,  H01L24/06 ,  H01L24/17 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/19105

Abstract: An electronic package is provided, including: a first circuit structure; an electronic component and a conductive pillar disposed on the first circuit structure; an encapsulation layer encapsulating the electronic component and the conductive pillar; a second circuit structure disposed on the encapsulation layer; and a shielding layer encapsulating the first circuit structure, a side surface of the encapsulation layer, and a side surface of the second circuit structure. The electronic component is surrounded by the shielding layer, and is protected from electromagnetic interference. A method for fabricating the electronic package is also provided.

公开(公告)号：US09607974B2

公开(公告)日：2017-03-28

申请号：US14940554

申请日：2015-11-13

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chun-Tang Lin ,  Shih-Ching Chen ,  Yi-Che Lai ,  Hong-Da Chang ,  Hung-Wen Liu ,  Yi-Wei Liu ,  Hsi-Chang Hsu

IPC: H01L25/00 ,  H01L25/065 ,  H01L21/683 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for fabricating a package structure is provided, which includes: providing a first carrier having a circuit layer thereon; forming a plurality of conductive posts on the circuit layer and disposing at least an electronic element on the first carrier; forming an encapsulant on the first carrier to encapsulate the conductive posts, the circuit layer and the electronic element; and removing the first carrier, thereby dispensing with the conventional hole opening process for forming the conductive posts and hence reducing the fabrication costs.

公开(公告)号：US20150344299A1

公开(公告)日：2015-12-03

申请号：US14821010

申请日：2015-08-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hong-Da Chang ,  Hsin-Yi Liao ,  Chun-An Huang ,  Shih-Kuang Chiu ,  Chien-An Chen

IPC: B81C1/00

CPC classification number: B81C1/00301 ,  B81B2201/0264 ,  B81C1/00269 ,  B81C2203/0154 ,  H01L29/84 ,  H01L2224/48091 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A wafer level package having a pressure sensor and a fabrication method thereof are provided. A wafer having the pressure sensor is bonded to a lid, and electrical connecting pads are formed on the wafer. After the lid is cut, wire-bonding and packaging processes are performed. Ends of bonding wires are exposed and serve as an electrical connecting path. A bottom opening is formed on a bottom surface of the wafer, in order to form a pressure sensor path.

Abstract translation: 提供了具有压力传感器及其制造方法的晶片级封装。 将具有压力传感器的晶片接合到盖上，并且在晶片上形成电连接焊盘。 在切割盖子之后，进行引线键合和封装处理。 接合线的端部暴露并用作电连接路径。 为了形成压力传感器路径，在晶片的底面上形成底部开口。

公开(公告)号：US20150041969A1

公开(公告)日：2015-02-12

申请号：US14074148

申请日：2013-11-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hong-Da Chang ,  Yi-Che Lai ,  Chi-Hsin Chiu ,  Shih-Kuang Chiu

IPC: H01L23/28 ,  H01L21/56

CPC classification number: H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a semiconductor structure having a carrier, a circuit portion formed on the carrier and a plurality of semiconductor elements disposed on the circuit portion; disposing a lamination member on the semiconductor elements; forming an insulating layer on the circuit portion for encapsulating the semiconductor elements; and removing the carrier. The lamination member increases the strength between adjacent semiconductor elements so as to overcome the conventional cracking problem caused by a CTE mismatch between the semiconductor elements and the insulating layer when the carrier is removed.

Abstract translation: 公开了一种半导体封装的制造方法，其包括以下步骤：提供具有载体的半导体结构，形成在载体上的电路部分和设置在电路部分上的多个半导体元件; 在所述半导体元件上设置层压部件; 在用于封装半导体元件的电路部分上形成绝缘层; 并移除载体。 层叠构件增加相邻半导体元件之间的强度，以克服当移除载体时由半导体元件和绝缘层之间的CTE失配引起的常规裂纹问题。