公开(公告)号：US20170221909A1

公开(公告)日：2017-08-03

申请号：US15489287

申请日：2017-04-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Harry-Hak-Lay Chuang ,  Chin-Yi Huang ,  Ya-Chen Kao

IPC分类号： H01L27/11507 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/66 ,  H01L27/11521 ,  H01L21/28 ,  H01L21/321

CPC分类号： H01L27/11507 ,  H01L21/28273 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/76229 ,  H01L27/11521 ,  H01L29/0649 ,  H01L29/66825

摘要： The present disclosure relates a method for manufacturing an integrated circuit. In some embodiments, a semiconductor substrate is provided and made up of a memory array region and a boundary region surrounding the memory array region. A hard mask layer is formed over the memory array region and the boundary region. The hard mask layer is patterned to form a boundary hard mask having one or more slots to expose some portions of the boundary region while the remaining regions of the boundary region are covered by the boundary hard mask. A floating gate layer is formed within the memory array region and extending over the hard mask layer. Then, a planarization is performed to reduce a height of the floating gate layer and form a plurality of floating gates.

公开(公告)号：US09679909B2

公开(公告)日：2017-06-13

申请号：US14750071

申请日：2015-06-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Harry-Hak-Lay Chuang ,  Yu-Hsiung Wang ,  Chen-Chin Liu

IPC分类号： H01L27/11 ,  H01L27/10 ,  H01L29/66 ,  H01L29/94 ,  H01L27/11575 ,  H01L27/1157

CPC分类号： H01L27/11575 ,  H01L27/0629 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/945

摘要： A method for forming a split-gate flash memory cell, and the resulting integrated circuit, are provided. A semiconductor substrate having memory cell and capacitor regions are provided. The capacitor region includes one or more sacrificial shallow trench isolation (STI) regions. A first etch is performed into the one or more sacrificial STI regions to remove the one or more sacrificial STI regions and to expose one or more trenches corresponding to the one or more sacrificial STI regions. Dopants are implanted into regions of the semiconductor substrate lining the one or more trenches. A conductive layer is formed filling the one or more trenches. A second etch is performed into the conductive layer to form one of a control gate and a select gate of a memory cell over the memory cell region, and to form an upper electrode of a finger trench capacitor over the capacitor region.

公开(公告)号：US09607121B2

公开(公告)日：2017-03-28

申请号：US14464730

申请日：2014-08-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Fu-Lung Hsueh ,  Chih-Ping Chao ,  Chewn-Pu Jou ,  Yung-Chow Peng ,  Harry-Hak-Lay Chuang ,  Kuo-Tung Sung

IPC分类号： G06F17/50 ,  H01L27/088 ,  H01L27/092

CPC分类号： G06F17/5068 ,  G06F17/50 ,  G06F17/5009 ,  H01L27/088 ,  H01L27/0922

摘要： A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage.

公开(公告)号：US09583591B2

公开(公告)日：2017-02-28

申请号：US14210796

申请日：2014-03-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Chin-Yi Huang ,  Shih-Chang Liu ,  Chang-Ming Wu

IPC分类号： H01L21/77 ,  H01L21/336 ,  H01L29/66 ,  H01L27/115

CPC分类号： H01L27/11534 ,  H01L27/11521 ,  H01L29/66545

摘要： The present disclosure relates to a method of embedding an ESF3 memory in a HKMG integrated circuit that utilizes a replacement gate technology. The ESF3 memory is formed over a recessed substrate which prevents damage of the memory control gates during the CMP process performed on the ILD layer. An asymmetric isolation zone is also formed in the transition region between the memory cell and the periphery circuit boundary.

摘要翻译： 本公开涉及一种在采用替代门技术的HKMG集成电路中嵌入ESF3存储器的方法。 ESF3存储器形成在凹陷的衬底上，防止在ILD层执行的CMP工艺期间对存储器控制栅极的损坏。 在存储单元和外围电路边界之间的过渡区域中也形成非对称隔离区。

公开(公告)号：US20160379988A1

公开(公告)日：2016-12-29

申请号：US14750071

申请日：2015-06-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Harry-Hak-Lay Chuang ,  Yu-Hsiung Wang ,  Chen-Chin Liu

IPC分类号： H01L27/115

CPC分类号： H01L27/11575 ,  H01L27/0629 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/945

摘要： A method for forming a split-gate flash memory cell, and the resulting integrated circuit, are provided. A semiconductor substrate having memory cell and capacitor regions are provided. The capacitor region includes one or more sacrificial shallow trench isolation (STI) regions. A first etch is performed into the one or more sacrificial STI regions to remove the one or more sacrificial STI regions and to expose one or more trenches corresponding to the one or more sacrificial STI regions. Dopants are implanted into regions of the semiconductor substrate lining the one or more trenches. A conductive layer is formed filling the one or more trenches. A second etch is performed into the conductive layer to form one of a control gate and a select gate of a memory cell over the memory cell region, and to form an upper electrode of a finger trench capacitor over the capacitor region.

摘要翻译： 提供了一种用于形成分裂栅极闪存单元的方法，以及所得到的集成电路。 提供了具有存储单元和电容器区域的半导体衬底。 电容器区域包括一个或多个牺牲浅沟槽隔离（STI）区域。 执行第一蚀刻到一个或多个牺牲STI区域中以去除一个或多个牺牲STI区域并暴露对应于一个或多个牺牲STI区域的一个或多个沟槽。 将掺杂剂注入衬在一个或多个沟槽上的半导体衬底的区域中。 形成填充一个或多个沟槽的导电层。 执行第二蚀刻到导电层中以在存储单元区域上形成存储单元的控制栅极和选择栅极之一，并且在电容器区域上形成手指沟槽电容器的上部电极。

公开(公告)号：US09502466B1

公开(公告)日：2016-11-22

申请号：US14810763

申请日：2015-07-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Harry-Hak-Lay Chuang ,  Wen-Chun You

IPC分类号： H01L27/00 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

CPC分类号： H01L27/2436 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

摘要： The present disclosure relates an integrated circuit (IC). The IC comprises a plurality of lower metal lines disposed within a lower inter-layer dielectric (ILD) layer over the substrate. The IC further comprises a plurality of memory cells disposed over the ILD layer and the lower metal lines at a memory region, a memory cell comprising a top electrode and a bottom electrode separated by a resistance switching element. The IC further comprises a dummy structure arranged directly above a first lower metal line at a logic region adjacent to the memory region, comprising a dummy bottom electrode and a dielectric mask on the dummy bottom electrode. The IC further comprises a top etch stop layer disposed on a bottom etch stop layer and extending upwardly along sidewalls of the dummy structure and overlying an upper surface of the dummy structure.

摘要翻译： 本发明涉及集成电路（IC）。 IC包括设置在衬底上的下层间电介质（ILD）层内的多个下金属线。 IC还包括设置在ILD层上的多个存储单元和存储区域中的下金属线，存储单元包括由电阻切换元件分离的顶电极和底电极。 IC还包括在与存储区域相邻的逻辑区域正下方布置的虚拟结构，在虚拟底部电极上包括虚拟底部电极和电介质掩模。 IC还包括顶部蚀刻停止层，其设置在底部蚀刻停止层上并沿虚拟结构的侧壁向上延伸并且覆盖在虚拟结构的上表面上。

公开(公告)号：US20150364575A1

公开(公告)日：2015-12-17

申请号：US14835958

申请日：2015-08-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei Cheng Wu ,  Kong-Pin Chang ,  Chia Ming Liang ,  Meng-Fang Hsu ,  Ching-Feng Fu ,  Shih-Ting Hung

IPC分类号： H01L29/66 ,  H01L21/762 ,  H01L21/8234

CPC分类号： H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7851

摘要： Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.

摘要翻译： 本公开的一些实施例涉及一种方法。 在该方法中，接收具有设置在半导体衬底中的有源区的半导体衬底。 形成浅沟槽隔离（STI）结构以横向围绕有源区域。 由STI结构限定的有源区的上表面凹入到STI结构的上表面的下方。 凹陷的上表面在STI结构的内侧壁之间连续延伸，并且使STI结构的内侧壁的上部露出。 在STI结构的内侧壁之间的有源区的凹面上外延生长半导体层。 在外延生长的半导体层上形成栅极电介质。 在栅极电介质上形成导电栅电极。

公开(公告)号：US20150236030A1

公开(公告)日：2015-08-20

申请号：US14182952

申请日：2014-02-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

CPC分类号： H01L29/42344 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/42324 ,  H01L29/42348 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

摘要： The present disclosure relates to a split gate memory device which requires less number of processing steps than traditional baseline processes and methods of making the same. Word gate/select gate (SG) pairs are formed around a sacrificial spacer. The resulting SG structure has a distinguishable non-planar top surface. The spacer layer that covers the select gate also follows the shape of the SG top surface. A dielectric disposed above the inter-gate dielectric layer and arranged between the neighboring sidewalls of the each memory gate and select gate provides isolation between them.

摘要翻译： 本公开涉及一种分裂门存储器件，其需要比传统的基线工艺更少数量的处理步骤及其制造方法。 字栅/选择栅极（SG）对围绕牺牲间隔物形成。 所得到的SG结构具有可区分的非平面顶表面。 覆盖选择栅的间隔层也遵循SG顶表面的形状。 设置在栅极间介电层上方并且布置在每个存储器栅极和选择栅极的相邻侧壁之间的电介质在它们之间提供隔离。

公开(公告)号：US11854828B2

公开(公告)日：2023-12-26

申请号：US17850643

申请日：2022-06-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Alexander Kalnitsky ,  Wei-Cheng Wu ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/8234 ,  H01L21/321 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L27/088

CPC分类号： H01L21/3212 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/4916 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/7816

摘要： A semiconductor device includes a substrate, a first well, a second well, a metal gate, a poly gate, a source region, and a drain region. The first well and the second well are within the substrate. The metal gate is partially over the first well. The poly gate is over the second well. The poly gate is separated from the metal gate, and a width ratio of the poly gate to the metal gate is in a range from about 0.1 to about 0.2. The source region and the drain region are respectively within the first well and the second well.

公开(公告)号：US11800724B2

公开(公告)日：2023-10-24

申请号：US17562949

申请日：2021-12-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Harry-Hak-Lay Chuang ,  Wen-Chun You ,  Hung Cho Wang ,  Yen-Yu Shih

IPC分类号： H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC分类号： H10B61/22 ,  H10N50/01 ,  H10N50/80

摘要： An MRAM memory cell includes a substrate and a transistor. The transistor includes: first and second source regions; a drain region between the first and second source regions; a first channel region between the drain region and the first source region; a second channel region between the drain region and the second source region; a first gate structure over the first channel region; and a second gate structure over the second channel region. A magnetic tunnel junction is overlying the transistor. The drain region is coupled to the magnetic tunnel junction. A first metal layer is overlying the transistor, and a second metal layer is overlying the first metal layer. The second and first metal layers couple a common source line signal to the first and second source regions of the MRAM memory cell and to those of a neighboring MRAM memory cell.