公开(公告)号：US20150255581A1

公开(公告)日：2015-09-10

申请号：US14199595

申请日：2014-03-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Chi Lin ,  Chin-Hsiang Lin ,  Neng-Kuo Chen ,  Sey-Ping Sun

IPC: H01L29/66 ,  H01L21/324 ,  H01L21/02 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/0234 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28255 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/513 ,  H01L29/517

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a substrate, the substrate includes a first fin, a second fin, and an isolation region disposed between the first fin and the second fin. The second fin includes a different material than a material of the substrate. The method includes forming an oxide over the first fin, the second fin, and a top surface of the isolation region at a temperature of about 400 degrees C. or less, and post-treating the oxide at a temperature of about 600 degrees C. or less.

Abstract translation: 公开了半导体器件及其制造方法。 在一些实施例中，制造半导体器件的方法包括提供衬底，所述衬底包括第一鳍片，第二鳍片和设置在第一鳍片和第二鳍片之间的隔离区域。 第二翅片包括与基底材料不同的材料。 该方法包括在约400℃或更低的温度下在隔离区的第一鳍片，第二鳍片和顶表面上形成氧化物，并在约600℃的温度下对氧化物进行后处理。 或更少。

公开(公告)号：US20140113424A1

公开(公告)日：2014-04-24

申请号：US14152400

申请日：2014-01-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Hsiang Lin ,  Jeff J. Xu ,  Pang-Yen Tsai

IPC: H01L29/66

CPC classification number: H01L29/66575 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/7849

Abstract: Various source/drain stressors that can enhance carrier mobility, and methods for manufacturing the same, are disclosed. An exemplary source/drain stressor includes a seed layer of a first material disposed over a substrate of a second material, the first material being different than the second material; a relaxed epitaxial layer disposed over the seed layer; and an epitaxial layer disposed over the relaxed epitaxial layer.

Abstract translation: 公开了可以增强载流子迁移率的各种源极/漏极应力源及其制造方法。 示例性源极/漏极应力器包括设置在第二材料的衬底上的第一材料的种子层，第一材料不同于第二材料; 设置在种子层上的松弛外延层; 以及设置在松弛外延层上的外延层。

公开(公告)号：US20130277769A1

公开(公告)日：2013-10-24

申请号：US13918684

申请日：2013-06-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hang Tung ,  Chin-Hsiang Lin ,  Cheng-Hung Chang ,  Sey-Ping Sun

IPC: H01L29/78

CPC classification number: H01L29/7856 ,  H01L29/41791 ,  H01L29/66803 ,  H01L29/7839 ,  H01L29/785 ,  H01L2029/7858

Abstract: Non-planar transistors and methods of fabrication thereof are described. In an embodiment, a method of forming a non-planar transistor includes forming a channel region on a first portion of a semiconductor fin, the semiconductor fin having a top surface and sidewalls. A gate electrode is formed over the channel region of the semiconductor fin, and an in-situ doped semiconductor layer is grown on the top surface and the sidewalls of the semiconductor fin on opposing sides of the gate electrode using a selective epitaxial growth process. At least a part of the doped semiconductor layer is converted to form a dopant rich region.

Abstract translation: 描述了非平面晶体管及其制造方法。 在一个实施例中，形成非平面晶体管的方法包括在半导体鳍片的第一部分上形成沟道区域，所述半导体鳍片具有顶表面和侧壁。 在半导体鳍片的沟道区域上形成栅电极，并且使用选择性外延生长工艺在栅电极的相对侧的半导体翅片的顶表面和侧壁上生长原位掺杂半导体层。 掺杂半导体层的至少一部分被转换以形成掺杂剂浓度区域。

公开(公告)号：US12222647B2

公开(公告)日：2025-02-11

申请号：US17873130

申请日：2022-07-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chun-Chih Ho ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/038 ,  G03F7/012 ,  G03F7/16

Abstract: A photoresist composition includes a conjugated resist additive, a photoactive compound, and a polymer resin. The conjugated resist additive is one or more selected from the group consisting of a polyacetylene, a polythiophene, a polyphenylenevinylene, a polyfluorene, a polypryrrole, a polyphenylene, and a polyaniline. The polyacetylene, polythiophene, polyphenylenevinylene, polyfluorene, polypryrrole, the polyphenylene, and polyaniline includes a substituent selected from the group consisting of an alkyl group, an ether group, an ester group, an alkene group, an aromatic group, an anthracene group, an alcohol group, an amine group, a carboxylic acid group, and an amide group. Another photoresist composition includes a polymer resin having a conjugated moiety and a photoactive compound. The conjugated moiety is one or more selected from the group consisting of a polyacetylene, a polythiophene, a polyphenylenevinylene, a polyfluorene, a polypryrrole, a polyphenylene, and a polyaniline.

公开(公告)号：US20240363726A1

公开(公告)日：2024-10-31

申请号：US18765932

申请日：2024-07-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Hsiang Lin ,  Teng-Chun TSAI ,  Huang-Lin Chao ,  Akira Mineji

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/321 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66515 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3212 ,  H01L29/45 ,  H01L29/4983 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.

公开(公告)号：US12087616B2

公开(公告)日：2024-09-10

申请号：US17720789

申请日：2022-04-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chun-Chih Ho ,  Yu-Chung Su ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/762 ,  H01L21/768

CPC classification number: H01L21/76289 ,  H01L21/76813

Abstract: A method of forming a semiconductor device includes forming a plurality of non-insulator structures on a substrate, the plurality of non-insulator structures being spaced apart by trenches, forming a sacrificial layer overfilling the trenches, reflowing the sacrificial layer at an elevated temperature, wherein a top surface of the sacrificial layer after the reflowing is lower than a top surface of the sacrificial layer before the reflowing, etching back the sacrificial layer to lower the top surface of the sacrificial layer to fall below top surfaces of the plurality of non-insulator structures, forming a dielectric layer on the sacrificial layer, and removing the sacrificial layer to form air gaps below the dielectric layer.

公开(公告)号：US11841619B2

公开(公告)日：2023-12-12

申请号：US17403816

申请日：2021-08-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsu-Ting Huang ,  Tung-Chin Wu ,  Shih-Hsiang Lo ,  Chih-Ming Lai ,  Jue-Chin Yu ,  Ru-Gun Liu ,  Chin-Hsiang Lin

IPC: G06F30/398 ,  G06F30/392 ,  G03F7/00 ,  G06F16/23 ,  G06N3/08 ,  G06N3/04

CPC classification number: G03F7/70441 ,  G06F16/2379 ,  G06F30/392 ,  G06F30/398 ,  G06N3/04 ,  G06N3/08

Abstract: A method for manufacturing a lithographic mask for an integrated circuit includes performing an optical proximity correction (OPC) process to an integrated circuit mask layout to produce a corrected mask layout. The method further includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout. The method also includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout.

公开(公告)号：US20230393467A1

公开(公告)日：2023-12-07

申请号：US18231444

申请日：2023-08-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY. LTD.

Inventor： Siao-Shan WANG ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/027 ,  G03F7/004 ,  G03F7/16 ,  G03F7/20

CPC classification number: G03F7/027 ,  G03F7/0045 ,  G03F7/168 ,  G03F7/2004 ,  C08L33/10

Abstract: A method for manufacturing a semiconductor device includes forming a photoresist layer including a photoresist composition over a substrate. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a patterned photoresist. The photoresist composition includes a photoactive compound and a resin comprising a radical-active functional group and an acid labile group.

公开(公告)号：US11821089B2

公开(公告)日：2023-11-21

申请号：US17034369

申请日：2020-09-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yen-Shuo Su ,  Ying Xiao ,  Chin-Hsiang Lin

IPC: C23C16/50 ,  C23C16/455 ,  H01J37/32 ,  C23C16/52

CPC classification number: C23C16/50 ,  C23C16/45561 ,  C23C16/45563 ,  C23C16/45565 ,  C23C16/52 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/32532 ,  H01J37/32899

Abstract: A control system for a plasma treatment apparatus includes a wafer treatment device. The wafer treatment device includes a vapor chamber and an upper electrode assembly. The upper electrode assembly includes a gas distribution plate having a plurality of holes. The upper electrode assembly includes an upper electrode having at least one gas nozzle and at least one controllable valve connected to the at least one gas nozzle for controlling a flow of gas from a gas supply to the holes via the at least one gas nozzle. The at least one gas nozzle is separated from the gate distribution plate by a gap. The control system includes a measurement device configured to measure a thickness profile of a wafer. The control system includes a controller configured to generate a control signal. The at least one controllable valve is configured to be adjusted based on the control signal.

公开(公告)号：US20230135538A1

公开(公告)日：2023-05-04

申请号：US17682623

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pei-Cheng Hsu ,  Ping-Huan Tsai ,  Huan-Ling Lee ,  Ta-Cheng Lien ,  Hsin-Chang Lee ,  Chin-Hsiang Lin

IPC: G03F1/64 ,  G03F7/20

Abstract: A pellicle assembly includes a pellicle membrane with a nanotube layer formed from nanotubes having a minimum length of 1,000 μm. The pellicle membrane can be formed with multiple layers and has a combination of high transmittance, low deflection, and small pore size. A conformal coating may applied to an outer surface of the pellicle membrane. The conformal coating is intended to protect the pellicle membrane from damage that can occur due to heat and hydrogen plasma created during EUV exposure.