公开(公告)号：US20150179452A1

公开(公告)日：2015-06-25

申请号：US14572936

申请日：2014-12-17

Applicant: Texas Instruments Incorporated

Inventor： Philip Leland HOWER ,  Sameer PENDHARKAR ,  Marie DENISON

IPC: H01L21/225 ,  H01L21/266 ,  H01L29/06 ,  H01L27/098 ,  H01L21/8232

CPC classification number: H01L29/808 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/32 ,  H01L21/8232 ,  H01L27/098 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0843 ,  H01L29/1058 ,  H01L29/36 ,  H01L29/66901

Abstract: An integrated circuit and method having a JFET with a buried drift layer and a buried channel in which the buried channel is formed by implanting through segmented implant areas so that the doping density of the buried channel is between 25 percent and 50 percent of the doping density of the buried drift layer.

Abstract translation: 一种集成电路和方法，其具有具有埋入漂移层的JFET和掩埋沟道，其中通过分段注入区域注入形成掩埋沟道，使得掩埋沟道的掺杂密度在掺杂密度的25％至50％之间 的埋层漂移层。

公开(公告)号：US20150097230A1

公开(公告)日：2015-04-09

申请号：US14044915

申请日：2013-10-03

Applicant: Texas Instruments Incorporated

Inventor： Marie DENISON ,  Sameer PENDHARKAR ,  Guru MATHUR

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L21/823487 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/51 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66734 ,  H01L29/7809

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

Abstract translation: 具有垂直漏极延伸MOS晶体管的半导体器件可以通过形成深沟槽结构以形成晶体管的垂直漂移区域而形成，使得每个垂直漂移区域通过深沟槽结构在至少两个相对侧上界定。 深沟槽结构被间隔开以形成漂移区域的RESURF区域。 在垂直漂移区域上的衬底中的沟槽中形成沟槽栅极。 身体区域位于垂直漂移区域上的衬底中。

公开(公告)号：US20140374766A1

公开(公告)日：2014-12-25

申请号：US13922352

申请日：2013-06-20

Applicant: Texas Instruments Incorporated

Inventor： Sandeep R. BAHL ,  Matthew SENESKY ,  Naveen TIPIRNENI ,  David I. ANDERSON ,  Sameer PENDHARKAR

IPC: H01L27/06 ,  H01L29/20

CPC classification number: H01L27/0629 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/8611 ,  H01L29/872 ,  H01L2224/48465

Abstract: A semiconductor device includes a bidirectional GaN FET formed on a non-insulating substrate. The semiconductor device further includes a first electrical clamp connected between the substrate and a first source/drain node of the bidirectional GaN FET, and a second electrical clamp connected between the substrate and a second source/drain node of the bidirectional GaN FET. The first clamp and the second clamp are configured to bias the substrate at a lower voltage level of an applied bias to the first source/drain node and an applied bias to the second source/drain node, within an offset voltage of the relevant clamp.

Abstract translation: 半导体器件包括形成在非绝缘衬底上的双向GaN FET。 所述半导体器件还包括连接在所述衬底和所述双向GaN FET的第一源极/漏极节点之间的第一电夹以及连接在所述衬底与所述双向GaN FET的第二源极/漏极节点之间的第二电夹。 第一钳位和第二钳位被配置为在施加的偏压的较低电压电平下将衬底偏置到第一源极/漏极节点，并在相关钳位的偏移电压内将施加的偏压施加到第二源极/漏极节点。

公开(公告)号：US20140183662A1

公开(公告)日：2014-07-03

申请号：US14101435

申请日：2013-12-10

Applicant: Texas Instruments Incorporated

Inventor： Yongxi ZHANG ,  Eugen MINDRICELU ,  Sameer PENDHARKAR ,  Seetharaman SRIDHAR

IPC: H01L27/02 ,  H01L21/761

CPC classification number: H01L21/761 ,  H01L21/823481 ,  H01L21/823493 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/0251

Abstract: An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type. A deep isolation trench is formed in the substrate through the deep well so as separate an unused portion of the deep well from a functional portion of the deep well. The functional portion of the deep well contains an active circuit element of the integrated circuit. The separated portion of the deep well does not contain an active circuit element. A contact region having the second conductivity type and a higher average doping density than the deep well is formed in the separated portion of the deep well. The contact region is connected to a voltage terminal of the integrated circuit.

Abstract translation: 在包含具有第一导电类型的半导体材料的基板上形成集成电路。 在第一导电类型的半导体材料中形成具有第二相对导电类型的深阱。 通过深井在衬底中形成深的隔离沟槽，以将深井的未使用部分与深井的功能部分分开。 深井的功能部分包含集成电路的有源电路元件。 深井的分离部分不包含有源电路元件。 在深井的分离部分中形成具有第二导电类型和比深阱更高的平均掺杂密度的接触区域。 接触区域连接到集成电路的电压端子。

公开(公告)号：US20240304719A1

公开(公告)日：2024-09-12

申请号：US18667032

申请日：2024-05-17

Applicant: Texas Instruments Incorporated

Inventor： Marie DENISON ,  Sameer PENDHARKAR ,  Guru MATHUR

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L21/823487 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/51 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/42368 ,  H01L29/4238

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

公开(公告)号：US20180240870A1

公开(公告)日：2018-08-23

申请号：US15955122

申请日：2018-04-17

Applicant: Texas Instruments Incorporated

Inventor： Marie DENISON ,  Philip L. HOWER ,  Sameer PENDHARKAR

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/40 ,  H01L21/225 ,  H01L29/10 ,  H01L21/324 ,  H01L21/761 ,  H01L29/423 ,  H01L21/266

CPC classification number: H01L29/0634 ,  H01L21/225 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L21/761 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7823 ,  H01L29/7835

Abstract: An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.

公开(公告)号：US20170222040A1

公开(公告)日：2017-08-03

申请号：US15485892

申请日：2017-04-12

Applicant: Texas Instruments Incorporated

Inventor： Marie DENISON ,  Sameer PENDHARKAR ,  Guru MATHUR

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/06 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L21/823487 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/51 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66734 ,  H01L29/7809

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

公开(公告)号：US20170062611A1

公开(公告)日：2017-03-02

申请号：US15348725

申请日：2016-11-10

Applicant: Texas Instruments Incorporated

Inventor： Yongxi ZHANG ,  Sameer PENDHARKAR ,  Seetharaman SRIDHAR

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L21/266 ,  H01L21/762

CPC classification number: H01L29/7823 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with the same conductivity type as the substrate, is disposed over the lower buried layer, so that electrical contact to the lower buried layer is made at a perimeter of the isolated device. The deep trench isolation laterally surrounds the isolated device. Electrical contact to the lower buried layer sufficient to maintain a desired bias to the lower buried layer is made along less than half of the perimeter of the isolated device, between the upper buried layer and the deep trench.

Abstract translation: 一种集成电路，包括隔离器件，隔离器件具有与深沟槽隔离相结合的较低埋层。 具有与衬底相同的导电类型的上掩埋层设置在下掩埋层上，使得在隔离器件的周边处形成与下掩埋层的电接触。 深沟槽隔离横向围绕隔离设备。 在下埋层之间的电接触足以保持对下掩埋层的期望偏压，沿着隔离器件的周边的上半部分在上掩埋层和深沟槽之间进行。

公开(公告)号：US20160277021A1

公开(公告)日：2016-09-22

申请号：US15168458

申请日：2016-05-31

Applicant: Texas Instruments Incorporated

Inventor： Sameer PENDHARKAR ,  Naveen TIPIRNENI

IPC: H03K17/687 ,  H01L27/092 ,  H01L29/66 ,  H01L27/088 ,  H01L29/20 ,  H01L29/78

CPC classification number: H03K17/6872 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/8236 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0883 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/7833 ,  H02M5/2573 ,  H03F3/193 ,  H03F3/195 ,  H03K17/6871 ,  H03K17/6877 ,  H03K2017/6875

Abstract: A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate.

公开(公告)号：US20150325578A1

公开(公告)日：2015-11-12

申请号：US14803678

申请日：2015-07-20

Applicant: Texas Instruments Incorporated

Inventor： Pinghai HAO ,  Sameer PENDHARKAR

IPC: H01L27/092 ,  H01L27/088 ,  H01L29/10 ,  H01L29/36 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823456 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/7835

Abstract: An integrated circuit containing an analog MOS transistor has an implant mask for a well which blocks well dopants from two diluted regions at edges of the gate, but exposes a channel region to the well dopants. A thermal drive step diffuses the implanted well dopants across the two diluted regions to form a continuous well with lower doping densities in the two diluted regions. Source/drain regions are formed adjacent to and underlapping the gate by implanting source/drain dopants into the substrate adjacent to the gate using the gate as a blocking layer and subsequently annealing the substrate so that the implanted source/drain dopants provide a desired extent of underlap of the source/drain regions under the gate. Drain extension dopants and halo dopants are not implanted into the substrate adjacent to the gate.

Abstract translation: 包含模拟MOS晶体管的集成电路具有用于阱的注入掩模，该掩模从栅极边缘处的两个稀释区域阻挡良好的掺杂剂，但是将沟道区域暴露于阱掺杂剂。 热驱动步骤将注入的阱掺杂物扩散到两个稀释区域上以在两个稀释区域中形成具有较低掺杂密度的连续阱。 通过使用栅极作为阻挡层将源极/漏极掺杂剂注入邻近栅极的衬底中，形成栅/漏区邻近并且使其重叠，随后使衬底退火，使得注入的源极/漏极掺杂剂提供期望的程度 栅极下的源极/漏极区的叠加。 漏极延伸掺杂剂和卤素掺杂剂不会被注入到与栅极相邻的衬底中。