公开(公告)号：US20150160285A1

公开(公告)日：2015-06-11

申请号：US14547849

申请日：2014-11-19

Applicant: Texas Instruments Incorporated

Inventor： Jungwoo Joh ,  Srikanth Krishnan ,  Sameer Pendharkar

IPC: G01R31/26 ,  H01L21/78 ,  H01L29/66 ,  H01L21/66

CPC classification number: G01R31/2621 ,  H01L29/2003 ,  H01L29/7787

Abstract: A method includes coupling a gate pulse generator to a gate terminal of a power transistor device under test, coupling a drain pulse generator to a drain terminal of the power transistor device under test; for a first set of test conditions, activating the drain pulse generator for each of the test conditions to apply a voltage pulse to the drain terminal, and for each of the test conditions, applying a voltage pulse to the gate terminal, the gate pulse rising only after the drain pulse falls below a predetermined threshold; for a second set of test conditions, applying a voltage pulse to the drain terminal, and applying a voltage pulse to the gate terminal, the drain pulse generator and the gate pulse generator both being active so that there is some overlap; and measuring the drain current into the power transistor device under test. An apparatus is disclosed.

Abstract translation: 一种方法包括将栅极脉冲发生器耦合到被测功率晶体管器件的栅极端子，将漏极脉冲发生器耦合到被测功率晶体管器件的漏极端子; 对于第一组测试条件，激活用于每个测试条件的漏极脉冲发生器以向漏极端施加电压脉冲，并且对于每个测试条件，向栅极端施加电压脉冲，门脉冲上升 仅在漏极脉冲下降到预定阈值以下之前; 对于第二组测试条件，向漏极端子施加电压脉冲，并向栅极端施加电压脉冲，漏极脉冲发生器和栅极脉冲发生器都处于活动状态，使得存在一些重叠; 并测量进入被测功率晶体管器件的漏极电流。 公开了一种装置。

公开(公告)号：US20150021687A1

公开(公告)日：2015-01-22

申请号：US13944864

申请日：2013-07-17

Applicant: Texas Instruments Incorporated

Inventor： Takehito Tamura ,  Binghua Hu ,  Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/06 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835

Abstract: The density of a transistor array is increased by forming one or more deep trench isolation structures in a semiconductor material. The deep trench isolation structures laterally surround the transistors in the array. The deep trench isolation structures limit the lateral diffusion of dopants and the lateral movement of charge carriers.

Abstract translation: 通过在半导体材料中形成一个或多个深沟槽隔离结构来增加晶体管阵列的密度。 深沟槽隔离结构横向围绕阵列中的晶体管。 深沟槽隔离结构限制了掺杂剂的横向扩散和载流子的横向移动。

公开(公告)号：US08749024B2

公开(公告)日：2014-06-10

申请号：US14073611

申请日：2013-11-06

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Marie Denison ,  Yongxi Zhang

IPC: H01L27/082

CPC classification number: H01L27/082 ,  H01L21/8222 ,  H01L27/0259 ,  H01L27/0823 ,  H01L29/735

Abstract: An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.

Abstract translation: 公开了一种包含串联连接的两个双极晶体管的叠层双极晶体管的集成电路。 每个双极晶体管包括击穿诱导特征。 击穿诱发特征相对于彼此具有反射对称性。 还公开了一种用于形成集成电路的方法，该集成电路包括具有串联连接的两个双极晶体管和具有反射对称性的击穿诱发特征的堆叠双极晶体管。

公开(公告)号：US20140061859A1

公开(公告)日：2014-03-06

申请号：US14073611

申请日：2013-11-06

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Marie Denison ,  Yongxi Zhang

IPC: H01L27/082

CPC classification number: H01L27/082 ,  H01L21/8222 ,  H01L27/0259 ,  H01L27/0823 ,  H01L29/735

Abstract: An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.

Abstract translation: 公开了一种包含串联连接的两个双极晶体管的叠层双极晶体管的集成电路。 每个双极晶体管包括击穿诱导特征。 击穿诱发特征相对于彼此具有反射对称性。 还公开了一种用于形成集成电路的方法，该集成电路包括具有串联连接的两个双极晶体管和具有反射对称性的击穿诱发特征的堆叠双极晶体管。

公开(公告)号：US20140061785A1

公开(公告)日：2014-03-06

申请号：US14073530

申请日：2013-11-06

Applicant: Texas Instruments Incorporated

Inventor： Philipp Steinmann ,  Amitava Chatterjee ,  Sameer Pendharkar

IPC: H01L29/08 ,  H01L29/78

CPC classification number: H01L29/66681 ,  G06F17/5081 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66659 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/861

Abstract: An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.

Abstract translation: 一种集成电路，其包含具有包含第一掺杂剂型和散射中心的漂移区的二极管。 一种包含DEMOS晶体管的集成电路，其具有包含第一掺杂剂型和散射中心的漂移区。 一种用于设计包含具有反掺杂漂移区的DEMOS晶体管的集成电路的方法。

公开(公告)号：US08530296B2

公开(公告)日：2013-09-10

申请号：US13765054

申请日：2013-02-12

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Sameer Pendharkar ,  Binghua Hu ,  Qingfeng Wang

IPC: H01L21/8238

CPC classification number: H01L29/0847 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/66659 ,  H01L29/7835

Abstract: An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations.

Abstract translation: 包含扩展漏极MOS晶体管的集成电路可以通过形成具有掩模手指的沟道区域的漂移区域注入掩模来形成，并且延伸到源极/沟道有源区，但不延伸到漏极接触有源区。 通过暴露的指状物注入的掺杂剂在掩模指下面的衬底中形成横向掺杂条纹。 栅极下方的漂移区域的平均掺杂密度比漏极接触有效面积处的漂移区域的平均掺杂密度小至少25％。 在一个实施例中，掺杂剂横向漫射以形成连续漂移区域。 在另一个实施例中，横向掺杂条纹之间的衬底材料与横向掺杂条纹保持相反的导电类型。

公开(公告)号：US12034074B2

公开(公告)日：2024-07-09

申请号：US17516017

申请日：2021-11-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Marie Denison ,  Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L21/823487 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/51 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/42368 ,  H01L29/4238

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

公开(公告)号：US11769824B2

公开(公告)日：2023-09-26

申请号：US17165697

申请日：2021-02-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Pinghai Hao ,  Sameer Pendharkar

IPC: H01L29/778 ,  H01L21/265 ,  H01L29/06 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/7786 ,  H01L21/2654 ,  H01L29/0603 ,  H01L29/0607 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/41775 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/0891 ,  H01L29/42316

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

公开(公告)号：US11456381B2

公开(公告)日：2022-09-27

申请号：US17123835

申请日：2020-12-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Meng-Chia Lee ,  Sunglyong Kim ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10

Abstract: Described examples include an integrated circuit having a semiconductor substrate. The integrated circuit has a transistor that includes a buried layer having within the substrate, the buried layer defining a drift region between the buried layer and the top surface and a body region in the substrate extending from the buried layer to the surface of the substrate. The transistor also having a source formed in the body region, a drain extending from the buried layer to the surface of the substrate, a drift well extending from the buried layer toward the top surface and extending from the body region to the drain, a drift surface layer located between the drift well and the top, and a gate proximate to the surface of the substrate at the body region.

公开(公告)号：US20220190158A1

公开(公告)日：2022-06-16

申请号：US17123835

申请日：2020-12-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Meng-Chia Lee ,  Sunglyong Kim ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66

Abstract: Described examples include an integrated circuit having a semiconductor substrate. The integrated circuit has a transistor that includes a buried layer having within the substrate, the buried layer defining a drift region between the buried layer and the top surface and a body region in the substrate extending from the buried layer to the surface of the substrate. The transistor also having a source formed in the body region, a drain extending from the buried layer to the surface of the substrate, a drift well extending from the buried layer toward the top surface and extending from the body region to the drain, a drift surface layer located between the drift well and the top, and a gate proximate to the surface of the substrate at the body region.