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    Semiconductor memory device for improving access time in burst mode
    21.
    发明申请
    Semiconductor memory device for improving access time in burst mode 有权
    用于在突发模式下改善访问时间的半导体存储器件

    公开(公告)号：US20050057996A1

    公开(公告)日：2005-03-17

    申请号：US10940777

    申请日：2004-09-15

    申请人： Tadaaki Yamauchi ,  Takashi Kubo

    发明人： Tadaaki Yamauchi ,  Takashi Kubo

    IPC分类号： G11C17/00 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00 ,  G11C8/04 ,  G11C16/26 ,  G11C16/32 ,  G11C17/12 ,  G11C17/18 ,  G11C29/00 ,  G11C29/04

    CPC分类号： G11C16/26 ,  G11C7/103 ,  G11C16/32 ,  G11C29/789 ,  G11C29/846

    摘要： A semiconductor memory device is disclosed. A block unit is divided into memory mats based on an internal address. In the case where the internal address is “1”, data are read in ascending order in accordance with a start address from the memory mat, while the internal address is incremented by an address conversion circuit thereby to select a 4-word block including the words next selected from the memory mat. At the same time, the internal address is incremented based on the start address, so that the period for reading each word included in the lowest order of 4-word block can be secured. In the process, the address next to be input can be decoded.

    摘要翻译： 公开了一种半导体存储器件。 块单元基于内部地址被分成存储器块。 在内部地址为“1”的情况下，根据来自存储器堆的开始地址按升序读取数据，而内部地址由地址转换电路递增，从而选择包含 从存储器垫子中选择的单词。 同时，内部地址根据起始地址增加，从而可以确保读取包含在4字块最低位的每个字的周期。 在此过程中，可以对接下来要输入的地址进行解码。

    Semiconductor device
    22.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US06744298B2

    公开(公告)日：2004-06-01

    申请号：US10209906

    申请日：2002-08-02

    申请人： Tadaaki Yamauchi ,  Takeo Okamoto ,  Junko Matsumoto

    发明人： Tadaaki Yamauchi ,  Takeo Okamoto ,  Junko Matsumoto

    IPC分类号： H03L500

    CPC分类号： G11C11/4072 ,  G11C7/20

    摘要： In the output circuit, at a subsequent stage of a gate circuit operating with a power supply voltage related to a first power supply voltage, a latch circuit formed of an inverter circuit and a MOS transistor is arranged, and is supplied with a second power supply voltage as an operating power supply voltage. An output buffer circuit is driven in accordance with an output signal of the latch circuit. When the first power supply voltage is powered down, the latch circuit receiving and operating with the second power supply voltage holds a signal voltage to be attained in a standby state and thus the output buffer circuit is reliably held in an output high impedance state. In a semiconductor device of a double power supply configuration, even when one power supply is powered down, the output buffer circuit can reliably be set to an output high impedance state.

    摘要翻译： 在输出电路中，在以与第一电源电压相关的电源电压工作的门电路的后续阶段，布置由逆变器电路和MOS晶体管形成的锁存电路，并且被提供有第二电源 电压作为工作电源电压。 根据锁存电路的输出信号驱动输出缓冲电路。 当第一电源电压断电时，以第二电源电压接收和操作的锁存电路在备用状态下保持要获得的信号电压，从而将输出缓冲电路可靠地保持在输出高阻抗状态。 在双电源配置的半导体器件中，即使当一个电源断电时，输出缓冲电路也可以可靠地设置为输出高阻抗状态。

    Semiconductor device
    24.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06717460B2

    公开(公告)日：2004-04-06

    申请号：US10211289

    申请日：2002-08-05

    申请人： Tadaaki Yamauchi ,  Takeo Okamoto ,  Junko Matsumoto ,  Zengcheng Tian

    发明人： Tadaaki Yamauchi ,  Takeo Okamoto ,  Junko Matsumoto ,  Zengcheng Tian

    IPC分类号： G05F110

    CPC分类号： G11C7/109 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074

    摘要： A level conversion circuit is provided, at an output, with an initialization circuit for setting the output signal of the level conversion circuit for generating a power cut enable signal controlling a deep power down mode to a predetermined inactive state upon power up. The initialization circuit is constituted by, for example, a capacitive element connected to the output node of the level conversion circuit to pull up the voltage of the output node upon power up, and a latch circuit latching the voltage level of the output node. When power is on, the power cut enable signal is forcibly inactivated by the initialization circuit to generate a periphery power supply voltage. The internal node of the level conversion circuit is initialized according to the output signal of a control circuit receiving the periphery power supply voltage as an operating power supply voltage. In semiconductor memory device having a deep power down mode, an internal voltage is generated reliably and properly upon power up of an internal voltage.

    摘要翻译： 在输出端提供电平转换电路，该初始化电路用于设置电平转换电路的输出信号，用于在上电时产生控制深度掉电模式至预定非活动状态的掉电使能信号。 初始化电路例如由与电平转换电路的输出节点连接的电容元件构成，以在上电时上拉输出节点的电压，以及锁存电路来锁存输出节点的电压电平。 当电源接通时，断电启动信号被初始化电路强制停用，以产生外围电源电压。 电平转换电路的内部节点根据接收外围电源电压的控制电路的输出信号作为工作电源电压进行初始化。 在具有深度掉电模式的半导体存储器件中，在内部电压上电时可靠且可靠地产生内部电压。

    Semiconductor memory device having a voltage lowering circuit of which supplying capability increases when column system is in operation
    26.
    发明授权
    Semiconductor memory device having a voltage lowering circuit of which supplying capability increases when column system is in operation 失效
    具有当列系统运行时供电能力增加的电压降低电路的半导体存储器件

    公开(公告)号：US5875145A

    公开(公告)日：1999-02-23

    申请号：US795529

    申请日：1997-02-05

    申请人： Kyoji Yamasaki ,  Tadaaki Yamauchi ,  Mikio Asakura

    发明人： Kyoji Yamasaki ,  Tadaaki Yamauchi ,  Mikio Asakura

    IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C1/34

    CPC分类号： G11C5/147

    摘要： A semiconductor memory device includes a memory cell array, peripheral circuits including a column decoder for connecting a word line, and a VDC circuit for peripherals, for generating an internal power supply voltage based on an external power supply voltage. VDC circuit for peripherals supplies the internal power supply voltage to peripheral circuits including the column decoder, other than the sense amplifier, output buffer and internal initial stage. The supplying capability of the VDC circuit for peripherals is increased in response to a VDCE signal which is output from a clock generation circuit when column decoder is activated. Therefore, even when power consumption in the peripheral circuit is increased as the column decoder is activated, sufficient power can be supplied to the peripheral circuit.

    摘要翻译： 半导体存储器件包括存储单元阵列，包括用于连接字线的列解码器和用于外围设备的VDC电路的外围电路，用于基于外部电源电压产生内部电源电压。 用于外设的VDC电路将内部电源电压提供给除了读出放大器，输出缓冲器和内部初始级之外的列解码器的外围电路。 响应于当列解码器被激活时从时钟发生电路输出的VDCE信号，外围设备的VDC电路的供应能力增加。 因此，即使当列解码器被激活时外围电路的功率消耗增加，也可以向外围电路提供足够的电力。

    CMOS substrate biasing for threshold voltage control
    27.
    发明授权
    CMOS substrate biasing for threshold voltage control 失效
    CMOS衬底偏置用于阈值电压控制

    公开(公告)号：US5838047A

    公开(公告)日：1998-11-17

    申请号：US663955

    申请日：1996-06-14

    申请人： Tadaaki Yamauchi ,  Kazutami Arimoto

    发明人： Tadaaki Yamauchi ,  Kazutami Arimoto

    IPC分类号： H01L21/822 ,  G11C11/408 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/04 ,  H01L27/092 ,  H03K19/0175 ,  H03K19/094 ,  H03K19/0948

    CPC分类号： H01L27/0218 ,  Y10S257/901

    摘要： A semiconductor device includes a PMOS transistor and an NMOS transistor. In a standby state, a potential of Vcc level is applied to the substrate of the PMOS transistor and a potential of Vss level is applied to the substrate of the NMOS transistor. Therefore, the voltage between the source and substrate of the P and NMOS transistors becomes 0 V. In an active state, potentials that render the voltage between the source and substrate lower than the built-in potential are applied to respective substrates of the P and NMOS transistors. Therefore, the threshold voltage of the transistor is lowered in an active state than in a standby state, and almost no leakage current flows between the source and substrate.

    摘要翻译： 半导体器件包括PMOS晶体管和NMOS晶体管。 在待机状态下，将Vcc电平的电位施加到PMOS晶体管的衬底，并且将Vss电平的电位施加到NMOS晶体管的衬底。 因此，P和NMOS晶体管的源极和衬底之间的电压变为0V。在有源状态下，使源极和衬底之间的电压低于内置电位的电位施加到P的相应衬底上， NMOS晶体管。 因此，晶体管的阈值电压在待机状态下处于活动状态，并且在源极和衬底之间几乎没有流过漏电流。

    Control signal generation circuit and semiconductor memory device that can correspond to high speed external clock signal
    28.
    发明授权
    Control signal generation circuit and semiconductor memory device that can correspond to high speed external clock signal 失效
    控制信号发生电路和半导体存储器件可以对应于高速外部时钟信号

    公开(公告)号：US5812492A

    公开(公告)日：1998-09-22

    申请号：US781013

    申请日：1997-01-10

    申请人： Tadaaki Yamauchi ,  Takaharu Tsuji ,  Mikio Asakura

    发明人： Tadaaki Yamauchi ,  Takaharu Tsuji ,  Mikio Asakura

    IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C8/00

    CPC分类号： G11C7/1045

    摘要： A semiconductor memory device operates switched between a first readout mode in which data readout according to a specified activation of a column address strobe signal /CAS that shows a transition in synchronization with an external clock signal is output during a period including the specified activation of signal /CAS, and a second readout mode in which the readout data is output during a subsequent predetermined period of signal /CAS. A control circuit for controlling the data output timing from an output buffer activates the output buffer at an elapse of a predetermined time following the specified activation of signal /CAS in the first readout mode. In the second readout mode, the control circuit activates the output buffer according to activation of signal /CAS at a predetermined period.

    摘要翻译： 半导体存储器件在第一读出模式之间切换，在第一读出模式中，在包括指定的信号激活的时段期间输出其中根据指示的激活表示与外部时钟信号同步的转换的列地址选通信号/ CAS的数据读出 / CAS，以及在信号/ CAS的后续预定周期期间输出读出数据的第二读出模式。 用于从输出缓冲器控制数据输出定时的控制电路在第一读出模式中指定的信号/ CAS激活之后经过预定时间激活输出缓冲器。 在第二读出模式中，控制电路根据信号/ CAS在预定周期的激活来激活输出缓冲器。