公开(公告)号：US20150021758A1

公开(公告)日：2015-01-22

申请号：US13943256

申请日：2013-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Hao TSAI ,  Chuei-Tang WANG ,  Chen-Hua YU

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02125 ,  H01L2224/02331 ,  H01L2224/02351 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/10145 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13006 ,  H01L2224/13014 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/1411 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2224/05669 ,  H01L2224/05666 ,  H01L2224/0346 ,  H01L2924/00012 ,  H01L2924/014

Abstract: Embodiments of mechanisms for forming a semiconductor die are provided. The semiconductor die includes a semiconductor substrate and a protection layer formed over the semiconductor substrate. The semiconductor die also includes a conductive layer conformally formed over the protection layer, and a recess is formed in the conductive layer. The recess surrounds a region of the conductive layer. The semiconductor die further includes a solder bump formed over the region of the conductive layer surrounded by the recess.

Abstract translation: 提供了用于形成半导体管芯的机构的实施例。 半导体管芯包括半导体衬底和形成在半导体衬底上的保护层。 半导体管芯还包括在保护层上保形地形成的导电层，并且在导电层中形成凹部。 凹部围绕导电层的区域。 半导体管芯还包括形成在由凹部包围的导电层的区域上的焊料凸块。

公开(公告)号：US20220384958A1

公开(公告)日：2022-12-01

申请号：US17885380

申请日：2022-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chuei-Tang WANG ,  Chung-Hao TSAI ,  Jeng-Shien HSIEH ,  Wei-Heng LIN ,  Kuo-Chung YEE ,  Chen-Hua YU

IPC: H01Q9/06 ,  H01Q1/22 ,  H01Q3/24 ,  H01Q1/36 ,  H01Q1/48

Abstract: An antenna device includes a radio frequency (RF) die, a first dielectric layer, a feeding line, a ground line, a second dielectric layer, and a radiating element. The first dielectric layer is over the RF die. The feeding line is in the first dielectric layer and is connected to the RF die. The ground line is in the first dielectric layer and is spaced apart from the feeding line. The second dielectric layer covers the first dielectric layer. The radiating element is over the second dielectric layer and is not in physically contact with the feeding line.

公开(公告)号：US20200058614A1

公开(公告)日：2020-02-20

申请号：US16373900

申请日：2019-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hang TUNG ,  Tung-Liang SHAO ,  Su-Chun YANG ,  Geng-Ming CHANG ,  Chen-Hua YU

IPC: H01L23/00

Abstract: A method for forming a chip package structure is provided. The method includes partially removing a first redistribution layer to form an alignment trench in the first redistribution layer. The alignment trench surrounds a bonding portion of the first redistribution layer. The method includes forming a liquid layer over the bonding portion. The method includes disposing a chip structure over the liquid layer, wherein a first width of the bonding portion is substantially equal to a second width of the chip structure. The method includes evaporating the liquid layer. The chip structure is in direct contact with the bonding portion after the liquid layer is evaporated.

公开(公告)号：US20190279951A1

公开(公告)日：2019-09-12

申请号：US16426365

申请日：2019-05-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yung-Ping CHIANG ,  Yi-Che CHIANG ,  Nien-Fang WU ,  Min-Chien HSIAO ,  Chao-Wen SHIH ,  Shou-Zen CHANG ,  Chung-Shi LIU ,  Chen-Hua YU

IPC: H01L23/66 ,  H01L23/552 ,  H01L23/00 ,  H01L21/683 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die.

公开(公告)号：US20190139865A1

公开(公告)日：2019-05-09

申请号：US16235365

申请日：2018-12-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Hua YU ,  Kuo-Chung YEE ,  Chun-Hui YU

IPC: H01L23/485 ,  H01L23/29 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L25/065 ,  H01L21/683

Abstract: Chip package structures are provided. The chip package structure includes a protection layer and a first chip disposed over the protection layer. The chip package structure further includes a first photosensitive layer formed around sidewalls of the first chip and covering a top surface of the first chip and a second chip disposed over the first photosensitive layer. In addition, the first chip and the second chip are separated by the first photosensitive layer.

公开(公告)号：US20190088544A1

公开(公告)日：2019-03-21

申请号：US15707534

申请日：2017-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua YU ,  Chuei-Tang WANG

IPC: H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first hole and a second hole in a first surface of a substrate. The method includes forming a first insulating layer in the first hole and the second hole. The method includes forming a conductive layer over the first insulating layer and in the first hole and the second hole. The method includes forming a second insulating layer over the conductive layer in the first recess. The second insulating layer has a second recess in the first recess. The method includes forming a conductive structure in the second recess. The method includes partially removing the substrate, the first insulating layer, the conductive layer, and the second insulating layer from a second surface of the substrate to expose the conductive structure and the conductive layer in the first hole and the second hole.

公开(公告)号：US20180151477A1

公开(公告)日：2018-05-31

申请号：US15372918

申请日：2016-12-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua YU ,  Kuo-Chung YEE ,  Chun-Hui YU

IPC: H01L23/485 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/485 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/293 ,  H01L23/3128 ,  H01L24/18 ,  H01L24/32 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/16225 ,  H01L2224/18 ,  H01L2224/32145

Abstract: Chip package structures and methods for forming the same are provided. The chip package structure includes a first protection layer and a first chip disposed over the first protection layer. The chip package structure further includes a first photosensitive layer surrounding the first chip and covering the first chip and a redistribution layer formed over the first photosensitive layer.

公开(公告)号：US20180138126A1

公开(公告)日：2018-05-17

申请号：US15355008

申请日：2016-11-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Lin CHEN ,  Chung-Hao TSAI ,  Jeng-Shien HSIEH ,  Chuei-Tang WANG ,  Chen-Hua YU ,  Chih-Yuan CHANG

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L21/768 ,  H01F27/245 ,  H01F27/28 ,  H01F41/02 ,  H01F41/04 ,  H01F41/12

Abstract: A package structure includes a first redistribution layer, a molding material, a semiconductor device and an inductor. The molding material is located on the first redistribution layer. The semiconductor device is molded in the molding material. The inductor penetrates through the molding material and electrically connected to the semiconductor device.

公开(公告)号：US20180108477A1

公开(公告)日：2018-04-19

申请号：US15707793

申请日：2017-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Monsen LIU ,  Chung-Hao TSAI ,  En-Hsiang YEH ,  Chuei-Tang WANG ,  Chen-Hua YU

IPC: H01F41/04 ,  H01R43/26 ,  H01R24/56 ,  H01F17/00 ,  H01F27/28 ,  H01R24/48 ,  H01R24/40 ,  H01L49/02 ,  H01L23/00 ,  H01L23/64 ,  H01L23/522 ,  H01L23/50

CPC classification number: H01F41/04 ,  H01F17/0006 ,  H01F27/2804 ,  H01F41/042 ,  H01F41/043 ,  H01F41/045 ,  H01F41/046 ,  H01F2027/2814 ,  H01L23/50 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/29 ,  H01L28/10 ,  H01R24/40 ,  H01R24/48 ,  H01R24/56 ,  H01R43/26 ,  Y10T29/4902 ,  Y10T29/49073 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49169

Abstract: A tunable three-dimensional (3D) inductor comprises a plurality of vias arranged with spacing among them, a plurality of interconnects in a metal layer, wherein the plurality of interconnects connect the plurality of vias on one end, and a plurality of tunable wires that connects to the plurality of vias on the other end to form the 3D inductor. The physical configuration and inductance value of the 3D inductor are adjustable by tuning the plurality of tunable wires during manufacturing process.

公开(公告)号：US20180012880A1

公开(公告)日：2018-01-11

申请号：US15205238

申请日：2016-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Chun YANG ,  Yi-Li HSIAO ,  Tung-Liang SHAO ,  Chih-Hang TUNG ,  Chen-Hua YU

IPC: H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/30604 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/18161

Abstract: Methods for forming a chip package are provided. The method includes providing at least one carrier substrate including first semiconductor dies mounted thereon. The method also includes forming a first noble metal layer including nanopores irregularly distributed therein to cover each one of the first semiconductor dies. The method further includes immersing the carrier substrate with the first semiconductor dies into an etchant solution including a fluoride etchant and an oxidizing agent, so that each one of the first semiconductor dies covered by the first noble metal layer is thinned.