公开(公告)号：US09620362B2

公开(公告)日：2017-04-11

申请号：US14699046

申请日：2015-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ming Chen ,  Chung-Yi Yu ,  Po-Chun Liu

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/205 ,  H01L29/778

CPC classification number: H01L21/02694 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/02617 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: The present disclosure relates to a structure and method of forming a GaN film on a Si substrate that includes an additional or second high temperature (HT) AlN seed layer, introduced for reducing the tensile stress of GaN on a Si substrate. The second HT AlN seed layer is disposed over a first HT AlN seed layer, and has a low V/III ratio compared to the first HT AlN seed layer. The second HT AlN seed layer has better lattice matching between Si and GaN and this reduces the tensile stress on GaN. The additional HT AlN seed layer further acts as a capping layer and helps annihilate or terminate threading dislocations (TDs) originating from a LT AlN seed layer. The second HT AlN seed layer also helps prevent Si diffusion from the substrate to the GaN film.

公开(公告)号：US20160240679A1

公开(公告)日：2016-08-18

申请号：US14620399

申请日：2015-02-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ming Chen ,  Chung-Yi Yu ,  Po-Chun Liu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/15 ,  H01L29/205

CPC classification number: H01L29/7849 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L29/1066 ,  H01L29/15 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/4236 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7786

Abstract: A transistor with a multi-strained layer superlattice (SLS) structure is provided. A first strained layer superlattice (SLS) layer is arranged over a substrate. A first buffer layer is arranged over the first SLS layer and includes dopants configured to increase a resistance of the first buffer layer. A second SLS layer is arranged over the first buffer layer. A second buffer layer is arranged over the second SLS layer and includes dopants configured to increase a resistance of the second buffer layer. A channel layer is arranged over the second buffer layer. An active layer is arranged over and directly abuts the channel layer. The channel and active layers collectively define a heterojunction. A method for manufacturing the transistor is also provided.

Abstract translation: 提供了具有多应变层超晶格（SLS）结构的晶体管。 第一应变层超晶格（SLS）层布置在衬底上。 第一缓冲层布置在第一SLS层之上，并且包括被配置为增加第一缓冲层的电阻的掺杂剂。 在第一缓冲层上布置第二SLS层。 第二缓冲层布置在第二SLS层上，并且包括被配置为增加第二缓冲层的电阻的掺杂剂。 沟道层布置在第二缓冲层上。 有源层布置在通道层上方并直接邻接通道层。 通道和有源层共同定义异质结。 还提供了制造晶体管的方法。

公开(公告)号：US09209190B2

公开(公告)日：2015-12-08

申请号：US13925984

申请日：2013-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Szu-Yu Wang ,  Chung-Yi Yu

IPC: H01L27/108 ,  H01L49/02 ,  H01L27/08

CPC classification number: H01L27/10829 ,  H01L24/73 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/91 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present disclosure relates to a method of forming a capacitor structure, including depositing a plurality of first polysilicon (POLY) layers of uniform thickness separated by a plurality of oxide/nitride/oxide (ONO) layers over a bottom and sidewalls of a recess and substrate surface. A second POLY layer is deposited over the plurality of first POLY layers, is separated by an ONO layer, and fills a remainder of the recess. Portions of the second POLY layer and the second ONO layer are removed with a first chemical-mechanical polish (CMP). A portion of each of the plurality of first POLY layers and the first ONO layers on the surface which are not within a doped region of the capacitor structure are removed with a first pattern and etch process such that a top surface of each of the plurality of first POLY layers is exposed for contact formation.

Abstract translation: 本公开涉及一种形成电容器结构的方法，包括在凹槽的底部和侧壁上沉积由多个氧化物/氮化物/氧化物（ONO）层隔开的多个均匀厚度的多个第一多晶硅（POLY）层，以及 基材表面。 第二POLY层沉积在多个第一POLY层上，被ONO层隔开，并填充凹槽的其余部分。 用第一化学机械抛光（CMP）去除第二POLY层和第二ONO层的部分。 多个第一POLY层和表面上不在电容器结构的掺杂区域内的第一ONO层的一部分用第一图案和蚀刻工艺去除，使得多个第一POLY层中的每一个的顶表面 第一POLY层被暴露以形成接触。

公开(公告)号：US20150069541A1

公开(公告)日：2015-03-12

申请号：US14023552

申请日：2013-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Chern-Yow Hsu ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L43/02 ,  H01L43/12

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/222 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.

Abstract translation: 本公开的一些实施例涉及一种实现具有低于某些光刻技术的较低分辨率极限的最小尺寸的磁性随机存取存储器（MRAM）单元的基本均匀图案的方法。 将包含第一和第二聚合物种类的共聚物溶液旋涂在位于基材表面上的异质结构上。 异质结构包括由绝缘层分开的第一和第二铁磁层。 将共聚物溶液自组装成包含第二聚合物种类的微畴图案的相分离材料在包含第一聚合物种类的聚合物基质内。 然后除去第一聚合物物质，留下第二聚合物物质的微畴图案。 通过在利用微畴图案作为硬掩模的同时蚀刻异质结构来形成异质结构内的磁记忆单元的图案。

公开(公告)号：US20140209920A1

公开(公告)日：2014-07-31

申请号：US13755058

申请日：2013-01-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Chun Liu ,  Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/66462 ,  H01L29/0843 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/7787

Abstract: The present disclosure relates to a channel layer of bi-layer of gallium nitride (GaN) within a HEMT. A first breakdown voltage layer of GaN is disposed beneath an active layer of the HEMT. A second breakdown voltage layer of GaN is disposed beneath the first breakdown voltage layer, wherein the first resistivity value is less than the second resistivity value. An increased resistivity of the second breakdown voltage layer results from an increased concentration of carbon dopants which increases the breakdown voltage in the second breakdown voltage layer, but can degrade the crystal structure. To alleviate this degradation, a crystal adaptation layer is disposed beneath the second breakdown voltage layer and configured to lattice-match to the second breakdown voltage layer of GaN. As a result, the HEMT achieves a high breakdown voltage without any associated degradation to the first breakdown voltage layer, wherein a channel of the HEMT resides.

Abstract translation: 本公开涉及HEMT内的氮化镓（GaN）双层的沟道层。 GaN的第一击穿电压层设置在HEMT的有源层的下方。 GaN的第二击穿电压层设置在第一击穿电压层的下方，其中第一电阻率值小于第二电阻率值。 第二击穿电压层的电阻率增加是由于增加了第二击穿电压层中的击穿电压但增加了晶体结构的碳掺杂剂的浓度增加。 为了减轻这种劣化，晶体适配层设置在第二击穿电压层之下，并被配置为与GaN的第二击穿电压层进行晶格匹配。 结果，HEMT实现了高的击穿电压，而没有与第一击穿电压层相关的任何相关的劣化，其中HEMT的通道驻留。

公开(公告)号：US20140209918A1

公开(公告)日：2014-07-31

申请号：US13749819

申请日：2013-01-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chi-Ming Chen ,  Po-Chun Liu ,  Chung-Yi Yu

IPC: H01L29/20 ,  H01L29/66

CPC classification number: H01L29/2003 ,  H01L29/42364 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7785 ,  H01L29/7787

Abstract: The present disclosure relates to a gallium-nitride (GaN) transistor device having a composite gallium nitride layer with alternating layers of GaN and aluminum nitride (AlN). In some embodiments, the GaN transistor device has a first GaN layer disposed above a semiconductor substrate. An AlN inter-layer is disposed on the first GaN layer. A second GaN layer is disposed on the AlN inter-layer. The AlN inter-layer allows for the thickness of the GaN layer to be increased over continuous GaN layers, mitigating bowing and cracking of the GaN substrate, while improving the breakdown voltage of the disclosed GaN device.

Abstract translation: 本公开涉及具有GaN和氮化铝（AlN）交替层的复合氮化镓层的氮化镓（GaN）晶体管器件。 在一些实施例中，GaN晶体管器件具有设置在半导体衬底之上的第一GaN层。 AlN层间设置在第一GaN层上。 第二GaN层设置在AlN层间。 AlN层间层允许GaN层的厚度在连续的GaN层上增加，减轻了GaN衬底的弯曲和破裂，同时改善了所公开的GaN器件的击穿电压。

公开(公告)号：US11515408B2

公开(公告)日：2022-11-29

申请号：US16806108

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuei-Ming Chen ,  Chi-Ming Chen ,  Chung-Yi Yu

IPC: H01L29/66 ,  H01L29/778 ,  H01L21/02

Abstract: Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

公开(公告)号：US11430729B2

公开(公告)日：2022-08-30

申请号：US17022320

申请日：2020-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Lien Lin ,  Cheng-Te Lee ,  Rei-Lin Chu ,  Chii-Ming Wu ,  Yeur-Luen Tu ,  Chung-Yi Yu

IPC: H01L23/522 ,  H01L27/08 ,  H01L49/02 ,  H01L21/02

Abstract: Various embodiments of the present application are directed towards a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode disposed over a semiconductor substrate. A top electrode is disposed over and overlies the bottom electrode. A capacitor insulator structure is disposed between the bottom electrode and the top electrode. The capacitor insulator structure comprises at least three dielectric structures vertically stacked upon each other. A bottom half of the capacitor insulator structure is a mirror image of a top half of the capacitor insulator structure in terms of dielectric materials of the dielectric structures.

公开(公告)号：US11232946B2

公开(公告)日：2022-01-25

申请号：US16786870

申请日：2020-02-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Rei-Lin Chu ,  Chih-Ming Chen ,  Chung-Yi Yu ,  Yeur-Luen Tu

IPC: H01L21/02 ,  H01L21/67 ,  H01L21/3065

Abstract: In accordance with some embodiments, a method for processing semiconductor wafer is provided. The method includes loading a semiconductor wafer into a chamber. The method also includes creating an exhaust flow from the chamber. The method further includes depositing a film on the semiconductor wafer by supplying a processing gas into the chamber. In addition, the method includes detecting, with a use of a gas sensor, a concentration of the processing gas in the exhaust flow and generating a detection signal according to a result of the detection. The method further includes supplying a cleaning gas into the processing chamber for a time period after the film is formed on the semiconductor wafer. The time period is determined based on the detection signal.

公开(公告)号：US20210391435A1

公开(公告)日：2021-12-16

申请号：US16901512

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ming Chen ,  Kuei-Ming Chen ,  Po-Chun Liu ,  Chung-Yi Yu

IPC: H01L29/423 ,  H01L29/788 ,  H01L29/78

Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.