公开(公告)号：US20230253464A1

公开(公告)日：2023-08-10

申请号：US18301113

申请日：2023-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  TsuChing Yang ,  Yu-Wei Jiang

IPC: H01L21/28 ,  G11C11/22 ,  H01L29/78 ,  H01L29/51 ,  H01L29/786

CPC classification number: H01L29/40111 ,  G11C11/223 ,  G11C11/2255 ,  H01L29/78391 ,  H01L29/516 ,  H01L29/7869 ,  G11C11/2257

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line. The dielectric material forms an interface with the OS layer. The dielectric material comprises hydrogen, and a hydrogen concentration at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at %).

公开(公告)号：US11723199B2

公开(公告)日：2023-08-08

申请号：US17190735

申请日：2021-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu Ching Yang ,  Sheng-Chih Lai ,  Yu-Wei Jiang ,  Kuo-Chang Chiang ,  Hung-Chang Sun ,  Chen-Jun Wu ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: H10B51/20 ,  H10B51/30 ,  H10B43/20 ,  H10B43/30

CPC classification number: H10B43/20 ,  H10B43/30 ,  H10B51/20 ,  H10B51/30

Abstract: A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.

公开(公告)号：US11705507B2

公开(公告)日：2023-07-18

申请号：US17333908

申请日：2021-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yao-Sheng Huang ,  Hung-Chang Sun ,  I-Ming Chang ,  Zi-Wei Fang

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/08 ,  H01L21/311 ,  H01L21/306

CPC classification number: H01L29/66795 ,  H01L21/0262 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02598 ,  H01L21/02639 ,  H01L21/02661 ,  H01L21/02675 ,  H01L21/31116 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/785 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/30604

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor fin extending from the semiconductor substrate, a gate structure extending across the semiconductor fin, and source/drain semiconductor layers on opposite sides of the gate structure. The source/drain semiconductor layers each have a first thickness over a top side of the semiconductor fin and a second thickness over a lateral side of the semiconductor fin. The first thickness and the second thickness have a difference smaller than about 20 percent of the first thickness.

公开(公告)号：US11688631B2

公开(公告)日：2023-06-27

申请号：US17859228

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chang Sun ,  Akira Mineji ,  Ziwei Fang

IPC: H01L21/764 ,  H01L29/51 ,  H01L29/66 ,  H01L21/265 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/266

CPC classification number: H01L21/764 ,  H01L21/266 ,  H01L21/26586 ,  H01L21/31053 ,  H01L21/31144 ,  H01L29/515 ,  H01L29/6656

Abstract: The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes receiving a substrate having an active region and an isolation region; forming gate stacks on the substrate that extends from the active region to the isolation region; forming an inner gate spacer and an outer gate spacer on sidewalls of the gate stacks; forming an interlevel dielectric (ILD) layer on the substrate; forming a mask layer over the substrate that exposes a portion of the ILD layer and a portion of the outer gate spacer; selectively etching the exposed portion of the outer gate spacer, resulting in an air gap between the inner gate spacer and the ILD layer; and performing an ion implantation process on the exposed portion of the ILD layer to seal the air gap.

公开(公告)号：US11640974B2

公开(公告)日：2023-05-02

申请号：US17119346

申请日：2020-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  Tsuching Yang ,  Yu-Wei Jiang

IPC: G11C11/22 ,  H01L21/28 ,  H01L29/786 ,  H01L29/78 ,  H01L29/51

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line. The dielectric material forms an interface with the OS layer. The dielectric material comprises hydrogen, and a hydrogen concentration at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at %).

公开(公告)号：US20220285384A1

公开(公告)日：2022-09-08

申请号：US17190735

申请日：2021-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu Ching Yang ,  Sheng-Chih Lai ,  Yu-Wei Jiang ,  Kuo-Chang Chiang ,  Hung-Chang Sun ,  Chen-Jun Wu ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: H01L27/11578 ,  H01L27/11568 ,  H01L27/1159 ,  H01L27/11597

Abstract: A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.

公开(公告)号：US20210082740A1

公开(公告)日：2021-03-18

申请号：US17106859

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chang Sun ,  Akira Mineji ,  Ziwei Fang

IPC: H01L21/764 ,  H01L29/51 ,  H01L29/66 ,  H01L21/265 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/266

Abstract: The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes receiving a substrate having an active region and an isolation region; forming gate stacks on the substrate and extending from the active region to the isolation region; forming an inner gate spacer and an outer gate spacer on sidewalls of the gate stacks; forming an interlevel dielectric (ILD) layer on the substrate; removing the outer gate spacer in the isolation region, resulting in an air gap between the inner gate spacer and the ILD layer; and performing an ion implantation process to the ILD layer, thereby expanding the ILD layer to cap the air gap.

公开(公告)号：US09960085B2

公开(公告)日：2018-05-01

申请号：US15001364

申请日：2016-01-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Pi Chang ,  Chih-Hao Wang ,  Wei-Hao Wu ,  Hung-Chang Sun ,  Lung-Kun Chu

IPC: H01L21/338 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/82345 ,  H01L27/092 ,  H01L29/4966

Abstract: The present disclosure relates to an integrated circuit with a work function metal layer disposed directly on a high-k dielectric layer, and an associated method of formation. In some embodiments, the integrated circuit is formed by forming a first work function metal layer directly on a high-k dielectric layer. Then the first work function metal layer is patterned to be left within a first gate region of a first device region and to be removed within a second gate region of a second device region. Thereby, the first work function metal layer is patterned directly on the high-k dielectric layer, using the high-k dielectric layer as an etch stop layer, and the patterning window is improved.

公开(公告)号：US12272750B2

公开(公告)日：2025-04-08

申请号：US18330604

申请日：2023-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  TsuChing Yang ,  Yu-Wei Jiang

IPC: G11C11/22 ,  G11C5/06 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786

Abstract: A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.

公开(公告)号：US12219777B2

公开(公告)日：2025-02-04

申请号：US18341116

申请日：2023-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  TsuChing Yang ,  Yu-Wei Jiang

IPC: H10B51/20 ,  G11C11/22 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line.