公开(公告)号：US20230207384A1

公开(公告)日：2023-06-29

申请号：US18178948

申请日：2023-03-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Kuo-Bin Huang ,  Neng-Jye Yang ,  Li-Min Chen

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/48 ,  H01L21/306

CPC classification number: H01L21/76823 ,  H01L21/02307 ,  H01L21/4857 ,  H01L21/30604 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

公开(公告)号：US20200105587A1

公开(公告)日：2020-04-02

申请号：US16145457

申请日：2018-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Kuo-Bin Huang ,  Neng-Jye Yang ,  Li-Min Chen

IPC: H01L21/768 ,  H01L21/306 ,  H01L21/48 ,  H01L21/02

Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

公开(公告)号：US12188686B2

公开(公告)日：2025-01-07

申请号：US17733657

申请日：2022-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Wei Wu ,  Hao Yang ,  Hsiao-Chieh Chou ,  Chun-Hung Chao ,  Jao Sheng Huang ,  Neng-Jye Yang ,  Kuo-Bin Huang

IPC: F24F9/00 ,  H01L21/67 ,  H01L21/687

Abstract: The present disclosure is at least directed to utilizing air curtain devices to form air curtains to separate and isolate areas in which respective workpieces are stored from a transfer compartment within a workpiece processing apparatus. The transfer compartment of the workpiece processing apparatus includes a robot configured to transfer or transport ones of the workpieces to and from these respective storage areas through the transfer compartment and to and from a tool compartment. A tool is present in the tool compartment for processing and refining the respective workpieces. Clean dry air (CDA) may be circulated through the respective storage areas. The air curtains formed by the air curtain devices and the circulation of CDA through the respective storage areas reduces the likelihood of the generation of defects, damages, and degradation of the workpieces when present within the workpiece processing apparatus.

公开(公告)号：US11990339B2

公开(公告)日：2024-05-21

申请号：US17391537

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Yao-Wen Hsu ,  Neng-Jye Yang ,  Li-Min Chen ,  Chia-Wei Wu ,  Kuan-Lin Chen ,  Kuo Bin Huang

IPC: H01L21/027 ,  G03F7/09 ,  G03F7/20 ,  G03F7/32 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  G03F7/095 ,  H01L21/306

CPC classification number: H01L21/0273 ,  G03F7/094 ,  G03F7/20 ,  G03F7/32 ,  H01L21/0228 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31111 ,  G03F7/095 ,  H01L21/30608

Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.

公开(公告)号：US20220277989A1

公开(公告)日：2022-09-01

申请号：US17745440

申请日：2022-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Wen Hsu ,  Ming-Che Ku ,  Neng-Jye Yang ,  Yu-Wen Wang

IPC: H01L21/768 ,  H01L21/02

Abstract: An opening is formed within a dielectric material overlying a semiconductor substrate. The opening may comprise a via portion and a trench portion. During the manufacturing process a treatment chemical is placed into contact with the exposed surfaces in order to release charges that have built up on the surfaces. By releasing the charges, a surface change potential difference is reduced, helping to prevent galvanic corrosion from occurring during further manufacturing.

公开(公告)号：US20210257218A1

公开(公告)日：2021-08-19

申请号：US17234119

申请日：2021-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan Hsuan Hsu ,  Jao Sheng Huang ,  Yen-Chiu Kuo ,  Yu-Li Cheng ,  Ya Tzu Chen ,  Neng-Jye Yang ,  Chun-Li Chou

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/67 ,  H01L21/687

Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.

公开(公告)号：US20210098290A1

公开(公告)日：2021-04-01

申请号：US16932208

申请日：2020-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiu-Wen Hsueh ,  Cai-Ling Wu ,  Ya-Ching Tseng ,  Chii-Ping Chen ,  Neng-Jye Yang

IPC: H01L21/768 ,  H01L23/522

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.

公开(公告)号：US10699944B2

公开(公告)日：2020-06-30

申请号：US16145457

申请日：2018-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Kuo-Bin Huang ,  Neng-Jye Yang ,  Li-Min Chen

IPC: H01L29/06 ,  H01L21/768 ,  H01L21/02 ,  H01L21/48 ,  H01L21/306

Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

公开(公告)号：US10676668B2

公开(公告)日：2020-06-09

申请号：US16220507

申请日：2018-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Neng-Jye Yang ,  Kuo Bin Huang ,  Ming-Hsi Yeh ,  Shun Wu Lin ,  Yu-Wen Wang ,  Jian-Jou Lian ,  Shih Min Chang

IPC: C09K13/02 ,  H01L29/66 ,  H01L21/3213 ,  C09K13/08 ,  C09K13/00

Abstract: For a metal gate replacement integration scheme, the present disclosure describes removing a polysilicon gate electrode with a highly selective wet etch chemistry without damaging surrounding layers. For example, the wet etch chemistry can include one or more alkaline solvents with a steric hindrance amine structure, a buffer system that includes tetramethylammonium hydroxide (TMAH) and monoethanolamine (MEA), one or more polar solvents, and water.

公开(公告)号：US10179878B2

公开(公告)日：2019-01-15

申请号：US15657537

申请日：2017-07-24

Applicant: Taiwan Semiconductor Manufacturing, Co., Ltd.

Inventor： Neng-Jye Yang ,  Kuo Bin Huang ,  Ming-Hsi Yeh ,  Shun Wu Lin ,  Yu-Wen Wang ,  Jian-Jou Lian ,  Shih Min Chang

IPC: H01L21/3213 ,  H01L29/66 ,  C09K13/08 ,  C09K13/02

Abstract: For a metal gate replacement integration scheme, the present disclosure describes removing a polysilicon gate electrode with a highly selective wet etch chemistry without damaging surrounding layers. For example, the wet etch chemistry can include one or more alkaline solvents with a steric hindrance amine structure, a buffer system that includes tetramethylammonium hydroxide (TMAH) and monoethanolamine (MEA), one or more polar solvents, and water.