公开(公告)号：US20240395598A1

公开(公告)日：2024-11-28

申请号：US18760573

申请日：2024-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiang-Bau Wang ,  Chun-Hung Lee

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

Abstract: A method for shallow trench isolation structures in a semiconductor device and a semiconductor device including the shallow trench isolation structures are disclosed. In an embodiment, the method may include forming a trench in a substrate; depositing a first dielectric liner in the trench; depositing a first shallow trench isolation (STI) material over the first dielectric liner, the first STI material being deposited as a conformal layer; etching the first STI material; depositing a second STI material over the first STI material, the second STI material being deposited as a flowable material; and planarizing the second STI material such that top surfaces of the second STI material are co-planar with top surfaces of the substrate.

公开(公告)号：US20240128126A1

公开(公告)日：2024-04-18

申请号：US18514661

申请日：2023-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Uei Jang ,  Chen-Huang Huang ,  Ryan Chia-Jen Chen ,  Shiang-Bau Wang ,  Shu-Yuan Ku

IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/308 ,  H01L21/762 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A conductive gate over a semiconductor fin is cut into a first conductive gate and a second conductive gate. An oxide is removed from sidewalls of the first conductive gate and a dielectric material is applied to the sidewalls. Spacers adjacent to the conductive gate are removed to form voids, and the voids are capped with a dielectric material to form air spacers.

公开(公告)号：US11349014B2

公开(公告)日：2022-05-31

申请号：US16917577

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Jhe Sie ,  Chen-Huang Huang ,  Shao-Hua Hsu ,  Cheng-Chung Chang ,  Szu-Ping Lee ,  An Chyi Wei ,  Shiang-Bau Wang ,  Chia-Jen Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/092

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.

公开(公告)号：US11094057B2

公开(公告)日：2021-08-17

申请号：US16984090

申请日：2020-08-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Peng-Ren Chen ,  Shiang-Bau Wang ,  Wen-Hao Cheng ,  Yung-Jung Chang ,  Wei-Chung Hu ,  Yi-An Huang ,  Jyun-Hong Chen

IPC: G06T7/00 ,  G06K9/62

Abstract: A method includes capturing a raw image from a semiconductor wafer, using graphic data system (GDS) information corresponding to the wafer to assign a measurement box in the raw image, performing a distance measurement on a feature of the raw image in the measurement box, and performing a manufacturing activity based on the distance measurement.

公开(公告)号：US20210074579A1

公开(公告)日：2021-03-11

申请号：US17101131

申请日：2020-11-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiang-Bau Wang ,  Chun-Hung Lee

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L21/3105

Abstract: A method for shallow trench isolation structures in a semiconductor device and a semiconductor device including the shallow trench isolation structures are disclosed. In an embodiment, the method may include forming a trench in a substrate; depositing a first dielectric liner in the trench; depositing a first shallow trench isolation (STI) material over the first dielectric liner, the first STI material being deposited as a conformal layer; etching the first STI material; depositing a second STI material over the first STI material, the second STI material being deposited as a flowable material; and planarizing the second STI material such that top surfaces of the second STI material are co-planar with top surfaces of the substrate.

公开(公告)号：US10762621B2

公开(公告)日：2020-09-01

申请号：US16400833

申请日：2019-05-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Peng-Ren Chen ,  Shiang-Bau Wang ,  Wen-Hao Cheng ,  Yung-Jung Chang ,  Wei-Chung Hu ,  Yi-An Huang ,  Jyun-Hong Chen

IPC: G06T7/00 ,  G06K9/62

Abstract: A method includes capturing a raw image from a semiconductor wafer, assigning a measurement box in the raw image, arranging a pair of indicators in the measurement box according to graphic data system (GDS) information of the semiconductor wafer, measuring a distance between the indicators, and performing a manufacturing activity based on the measured distance.

公开(公告)号：US10707072B2

公开(公告)日：2020-07-07

申请号：US16231728

申请日：2018-12-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shiang-Bau Wang

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/51 ,  H01L29/267 ,  H01L29/78 ,  H01L29/165

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a first fin structure and a second fin structure formed over the substrate. The semiconductor structure further includes an isolation structure formed adjacent to the second fin structure and covering the first fin structure and a gate structure formed over the first fin structure and the second fin structure. In addition, the first fin structure is lower than the second fin structure, and the first fin structure has a curved top surface under the isolation structure.

公开(公告)号：US10304178B2

公开(公告)日：2019-05-28

申请号：US14858049

申请日：2015-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Peng-Ren Chen ,  Shiang-Bau Wang ,  Wen-Hao Cheng ,  Yung-Jung Chang ,  Wei-Chung Hu ,  Yi-An Huang ,  Jyun-Hong Chen

IPC: G06K9/62 ,  G06T7/00

Abstract: Methods and systems for diagnosing semiconductor wafer are provided. A target image is obtained according to graphic data system (GDS) information of a specific layout in the semiconductor wafer, wherein the target image includes a first contour having a first pattern corresponding to the specific layout. Image-based alignment is performed to capture a raw image from the semiconductor wafer according to the first contour. The semiconductor wafer is analyzed by measuring the raw image, so as to provide a diagnostic result.

公开(公告)号：US09824940B2

公开(公告)日：2017-11-21

申请号：US14923607

申请日：2015-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiang-Bau Wang ,  Victor Y. Lu

IPC: H01L21/66 ,  G01B11/06 ,  H01L21/67 ,  H01L21/027 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3065

CPC classification number: H01L22/20 ,  G01B11/0616 ,  G01B11/0675 ,  G01B2210/56 ,  G03F7/70616 ,  G03F7/70625 ,  H01L21/0273 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/67253 ,  H01L22/12

Abstract: A method for intelligent inline metrology is a provided. A parameter of a workpiece is measured at a first set of inspection sites on the workpiece. A determination is made as to whether a first specification is met using the measurements at the first set of inspection sites. In response to the first specification being met, the parameter is estimated at a second set of inspection sites on the workpiece. In response to the first specification being unmet, the parameter is measured at the second set of inspection sites and a determination is made as to whether a second specification is met using the measurements at the second set of inspection sites. A system for intelligent inline metrology is also provided.

公开(公告)号：US09691587B2

公开(公告)日：2017-06-27

申请号：US14319071

申请日：2014-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Shiang-Bau Wang

IPC: H01L21/02 ,  H01L21/311 ,  H01J37/26 ,  H01L21/66

CPC classification number: H01J37/261 ,  H01J37/3178 ,  H01L22/12 ,  H01L22/30

Abstract: A method for forming a dimension measurement apparatus calibration standard over a substrate is provided. The method includes forming strip structures over the substrate. The method includes depositing a calibration material layer over the substrate and the strip structures. The calibration material layer and the strip structures are made of different materials. The method includes removing the calibration material layer over top surfaces of the strip structures to expose the strip structures. The method includes removing the strip structures. The calibration material layer remaining over sidewalls of the strip structures forms linear calibration structures.