公开(公告)号：US09659953B2

公开(公告)日：2017-05-23

申请号：US14324369

申请日：2014-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Yi Hsien Lu

IPC: H01L27/115 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L27/11573 ,  H01L29/51 ,  H01L27/088

CPC classification number: H01L27/11573 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656

Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-κ metal gate) integrated circuit which includes a high voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.

公开(公告)号：US20160181268A1

公开(公告)日：2016-06-23

申请号：US14580454

申请日：2014-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Fang-Lan Chu

IPC: H01L27/115

CPC classification number: H01L27/11573 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11575 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure relates to a structure and method for reducing CMP dishing in integrated circuits. In some embodiments, the structure has a semiconductor substrate with an embedded memory region and a periphery region. one or more dummy structures are formed between the memory region and the periphery region. Placement of the dummy structures between the embedded memory region and the periphery region causes the surface of a deposition layer therebetween to become more planar after being polished without resulting in a dishing effect. The reduced recess reduces metal residue formation and thus leakage and shorting of current due to metal residue. Further, less dishing will reduce the polysilicon loss of active devices. In some embodiments, one of the dummy structures is formed with an angled sidewall which eliminates the need for a boundary cut etch process.

Abstract translation: 本公开涉及用于减少集成电路中的CMP凹陷的结构和方法。 在一些实施例中，该结构具有具有嵌入的存储区域和外围区域的半导体衬底。 在存储区域和外围区域之间形成一个或多个虚拟结构。 在嵌入的存储区域和外围区域之间的虚拟结构的放置使得其之间的沉积层的表面在抛光之后变得更平坦，而不会产生凹陷效应。 减少的凹陷减少金属残留物的形成，从而导致金属残留物导致的电流泄漏和短路。 此外，较少的凹陷将减少有源器件的多晶硅损耗。 在一些实施例中，虚拟结构之一形成有成角度的侧壁，其消除了对边界切割蚀刻工艺的需要。

公开(公告)号：US20160133636A1

公开(公告)日：2016-05-12

申请号：US14980147

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu

IPC: H01L27/115 ,  H01L21/321 ,  H01L21/306 ,  H01L21/28

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/3212 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1116 ,  H01L27/11546 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/66545

Abstract: An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.

Abstract translation: 嵌入式闪速存储器件包括栅堆叠，其包括延伸到半导体衬底中的凹部中的底部电介质层和位于底部电介质层上的电荷存储层。 电荷存储层包括凹部中的一部分。 栅极堆叠还包括电荷存储层上的顶部电介质层，以及在顶部电介质层上方的金属栅极。 源极和漏极区位于半导体衬底中，并且位于栅堆叠的相对侧上。

公开(公告)号：US09287279B2

公开(公告)日：2016-03-15

申请号：US14225874

申请日：2014-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsing Chang ,  Chang-Ming Wu ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Wei Cheng Wu ,  Harry-Hak-Lay Chuang

IPC: H01L27/115 ,  H01L29/788 ,  H01L21/28

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7883

Abstract: Some embodiments relate to a memory cell with a charge-trapping layer of nanocrystals, comprising a tunneling oxide layer along a select gate, a control oxide layer formed between a control gate and the tunnel oxide layer, and a plurality of nanocrystals arranged between the tunneling and control oxide layers. An encapsulating layer isolates the nanocrystals from the control oxide layer. Contact formation to the select gate includes a two-step etch. A first etch includes a selectivity between oxide and the encapsulating layer, and etches away the control oxide layer while leaving the encapsulating layer intact. A second etch, which has an opposite selectivity of the first etch, then etches away the encapsulating layer while leaving the tunneling oxide layer intact. As a result, the control oxide layer and nanocrystals are etched away from a surface of the select gate, while leaving the tunneling oxide layer intact for contact isolation.

Abstract translation: 一些实施例涉及具有纳米晶体的电荷捕获层的存储器单元，其包括沿着选择栅极的隧穿氧化物层，形成在控制栅极和隧道氧化物层之间的控制氧化物层，以及多个纳米晶体，其布置在隧道 并控制氧化物层。 封装层将纳米晶体与控制氧化物层隔离。 与选择栅极的接触形成包括两步蚀刻。 第一蚀刻包括氧化物和封装层之间的选择性，并且蚀刻掉控制氧化物层，同时保持封装层完好无损。 具有与第一蚀刻相反的选择性的第二蚀刻然后在完全留下隧道氧化物层的同时蚀刻封装层。 结果，将控制氧化物层和纳米晶体从选择栅极的表面蚀刻掉，同时使隧道氧化物层完好无损以进行接触隔离。

公开(公告)号：US20160020219A1

公开(公告)日：2016-01-21

申请号：US14332556

申请日：2014-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Kai-Shyang You

IPC: H01L27/115 ,  H01L29/423 ,  H01L21/265 ,  H01L29/06 ,  H01L29/49 ,  H01L21/28 ,  H01L27/12 ,  H01L29/51

CPC classification number: H01L21/265 ,  H01L21/26513 ,  H01L21/28017 ,  H01L21/28282 ,  H01L27/11573 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/42344 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/78 ,  H01L29/792

Abstract: Some embodiments of the present disclosure provide an integrated circuit arranged on a silicon-on-insulator (SOI) substrate region. The SOI substrate region is made up of a handle wafer region, an oxide layer arranged over the handle wafer region, and a silicon layer arranged over the oxide layer. A recess extends downward from an upper surface of the silicon layer and terminates in the handle wafer region, thereby defining a recessed handle wafer surface and sidewalls extending upwardly from the recessed handle wafer surface to meet the upper surface of the silicon layer. A first semiconductor device is disposed on the recessed handle wafer surface. A second semiconductor device is disposed on the upper surface of the silicon layer.

Abstract translation: 本公开的一些实施例提供了布置在绝缘体上硅（SOI）衬底区域上的集成电路。 SOI衬底区域由处理晶片区域，布置在处理晶片区域上的氧化物层和布置在氧化物层上的硅层构成。 凹部从硅层的上表面向下延伸并且终止于处理晶片区域，从而限定凹入的处理晶片表面和从凹入的处理晶片表面向上延伸以与硅层的上表面相遇的侧壁。 第一半导体器件设置在凹入的处理晶片表面上。 第二半导体器件设置在硅层的上表面上。

公开(公告)号：US20160005756A1

公开(公告)日：2016-01-07

申请号：US14324369

申请日：2014-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Yi Hsien Lu

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/11573 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656

Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-κ metal gate) integrated circuit which includes a high voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.

Abstract translation: 本公开涉及一种用于在包括高电压（HV）HKMG晶体管的HKMG（高金属栅极）集成电路中嵌入非易失性存储器（NVM）的结构和方法。 NVM设备（例如，闪速存储器）在高电压下操作用于其读取和写入操作，因此HV器件对于涉及非易失性嵌入式存储器和HKMG逻辑电路的集成电路是必需的。 与HKMG外围电路一起形成HV HKMG电路减少了HV晶体管与外围电路的其余部分之间的附加边界的需要。 该方法进一步有助于减少divot问题并减少单元大小。

公开(公告)号：US11856767B2

公开(公告)日：2023-12-26

申请号：US17374573

申请日：2021-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Wei Cheng Wu

IPC: H10B41/30 ,  H10B41/40

CPC classification number: H10B41/30 ,  H10B41/40

Abstract: A method includes planarizing a protective layer over gate materials overlying a recessed region in a substrate. The planarizing includes forming a first planarized surface by planarizing a sacrificial layer over the protective layer, and forming a second planarized surface of the protective layer by etching the first planarized surface of the sacrificial layer at an even rate across the recessed region. An etch mask layer is formed over the second planarized surface, and control gate stacks are formed in the recessed region by etching the gate materials.

公开(公告)号：US11758721B2

公开(公告)日：2023-09-12

申请号：US17202193

申请日：2021-03-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei Cheng Wu ,  Li-Feng Teng

IPC: H10B41/42 ,  H01L29/66 ,  H01L21/28 ,  H10B41/00 ,  H10B41/20 ,  H10B41/30 ,  H10B41/40 ,  H10B41/44 ,  H10B41/46 ,  H10B41/50 ,  H10B69/00 ,  H01L29/423

CPC classification number: H10B41/42 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/66825 ,  H10B41/00 ,  H10B41/20 ,  H10B41/30 ,  H10B41/40 ,  H10B41/44 ,  H10B41/46 ,  H10B41/50 ,  H10B69/00

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate. A second dielectric layer is disposed between the floating gate and the control gate, having one of a silicon nitride layer, a silicon oxide layer and multilayers thereof. A third dielectric layer is disposed between the second dielectric layer and the control gate, and includes a dielectric material having a dielectric constant higher than silicon nitride.

公开(公告)号：US11594620B2

公开(公告)日：2023-02-28

申请号：US17202170

申请日：2021-03-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei Cheng Wu ,  Li-Feng Teng

IPC: H01L29/66 ,  H01L21/28 ,  H01L27/11546 ,  H01L21/762 ,  H01L27/11521 ,  H01L27/11531 ,  H01L27/11548 ,  H01L29/06 ,  H01L29/423 ,  H01L29/788

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate and having one of a silicon oxide layer, a silicon nitride layer and multilayers of silicon oxide and silicon nitride, and an erase gate and a select gate. The erase gate and the select gate include a stack of a bottom polysilicon layer and an upper metal layer.

公开(公告)号：US11264400B2

公开(公告)日：2022-03-01

申请号：US16950144

申请日：2020-11-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Jui-Tsung Lien

IPC: H01L27/1157 ,  H01L21/28 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

Abstract: In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The channel region includes a first portion adjacent to the first source/drain region and a second portion adjacent the second source/drain region. A select gate is spaced over the first portion of the channel region and is separated from the first portion of the channel region by a select gate dielectric. A memory gate is spaced over the second portion of the channel region and is separated from the second portion of the channel region by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly alongside the memory gate to separate neighboring sidewalls of the select gate and memory gate from one another. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the second source/drain region.