公开(公告)号：US20210217726A1

公开(公告)日：2021-07-15

申请号：US17215555

申请日：2021-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Der-Chyang Yeh ,  Kuo-Chung Yee ,  Jui-Pin Hung

IPC: H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L25/10 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/78 ,  H01L23/31 ,  H01L23/48

Abstract: A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die.

公开(公告)号：US20210183813A1

公开(公告)日：2021-06-17

申请号：US16718073

申请日：2019-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Der-Chyang Yeh ,  Li-Hsien Huang ,  Ta-Hsuan Lin ,  Ming-Shih Yeh

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor structure includes a semiconductor structure includes a semiconductor die, an insulating encapsulation, a passivation layer and conductive elements. The semiconductor die includes a sensor device and a semiconductor substrate with a first region and a second region adjacent to the first region, and the sensor device is embedded in the semiconductor substrate within the first region. The insulating encapsulation laterally encapsulates the semiconductor die and covers a sidewall of the semiconductor die. The passivation layer is located on the semiconductor die, wherein a recess penetrates through the passivation layer over the first region and is overlapped with the sensor device. The conductive elements are located on the passivation layer over the second region and are electrically connected to the semiconductor die, wherein the passivation layer is between the insulating encapsulation and the conductive elements.

公开(公告)号：US20210035953A1

公开(公告)日：2021-02-04

申请号：US17073888

申请日：2020-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Wei-Yu Chen ,  Ying-Ju Chen ,  Tsung-Shu Lin ,  Chin-Chuan Chang ,  Hsien-Wei Chen ,  Wei-Cheng Wu ,  Li-Hsien Huang ,  Chi-Hsi Wu ,  Der-Chyang Yeh

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.

公开(公告)号：US10475731B2

公开(公告)日：2019-11-12

申请号：US16371356

申请日：2019-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuo-Mao Chen ,  Der-Chyang Yeh ,  Chiung-Han Yeh

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31

Abstract: A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.

公开(公告)号：US09911672B1

公开(公告)日：2018-03-06

申请号：US15281086

申请日：2016-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Hsi Wu ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Li-Hsien Huang ,  Kuan-Chung Lu

IPC: H01L21/66 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/498 ,  H01L23/31 ,  H01L25/10 ,  H01L25/065

CPC classification number: H01L22/32 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/18 ,  H01L2224/48091 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1058 ,  H01L2924/00014

Abstract: A semiconductor device including an integrated circuit, a plurality of conductive pillars, and a protection layer is provided. The integrated circuit includes a semiconductor substrate and an interconnection structure covering the semiconductor substrate, wherein the interconnection structure includes a plurality of patterned conductive layers and a plurality of inter-dielectric layers stacked alternately, the topmost patterned conductive layer of the patterned conductive layers is covered by the topmost inter-dielectric layer of the inter-dielectric layers, and the topmost patterned conductive layer is exposed by a plurality of openings of the topmost inter-dielectric layer. The conductive pillars are disposed on the topmost patterned conductive layer exposed by the openings, and the conductive pillars are electrically connected to the topmost patterned conductive layer through the openings. The protection layer covers the integrated circuit and the conductive pillars. A method for fabricating the semiconductor device and a method for fabricating integrated fan-out packages including the semiconductor device are also provided.

公开(公告)号：US20170278827A1

公开(公告)日：2017-09-28

申请号：US15622166

申请日：2017-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Der-Chyang Yeh

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/34 ,  H01L23/36 ,  H01L23/373 ,  H01L23/498 ,  H01L23/58 ,  H01L25/00 ,  H01L25/03

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/34 ,  H01L23/36 ,  H01L23/3737 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/585 ,  H01L24/19 ,  H01L24/29 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/26125 ,  H01L2224/26145 ,  H01L2224/26155 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/325 ,  H01L2224/33505 ,  H01L2224/33519 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81007 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2224/19 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a substrate. A first die is coupled beneath a lower surface of the substrate. A second die is coupled beneath the lower surface of the substrate and is disposed over the first die. A thermal contact pad is arranged beneath a lower surface of the second die and an upper surface of the first die. The thermal contact pad thermally isolates the first die from the second die.

公开(公告)号：US09685426B2

公开(公告)日：2017-06-20

申请号：US15170036

申请日：2016-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Der-Chyang Yeh

IPC: H01L25/065 ,  H01L23/34 ,  H01L21/56 ,  H01L25/00 ,  H01L23/00 ,  H01L21/683 ,  H01L23/58 ,  H01L23/31 ,  H01L23/36 ,  H01L23/373 ,  H01L23/498 ,  H01L25/03

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/34 ,  H01L23/36 ,  H01L23/3737 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/585 ,  H01L24/19 ,  H01L24/29 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/26125 ,  H01L2224/26145 ,  H01L2224/26155 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/325 ,  H01L2224/33505 ,  H01L2224/33519 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81007 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2224/19 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a substrate and a first die coupled to a top surface of the substrate. A second die is coupled to a bottom surface of the substrate. A thermal contact pad couples the second die to the bottom surface of the substrate. The thermal contact pad electrically isolates the first die from the second die. A molding compound resides over the substrate and surrounds the first and second dies and the thermal contact pad.

公开(公告)号：US20160118301A1

公开(公告)日：2016-04-28

申请号：US14990976

申请日：2016-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Shang-Yun Hou ,  Wen-Chih Chiou ,  Jui-Pin Hung ,  Der-Chyang Yeh ,  Chiung-Han Yeh

IPC: H01L21/78 ,  H01L49/02 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L21/78 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/5223 ,  H01L23/525 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L27/1255 ,  H01L27/3276 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2224/82 ,  H01L2924/00

Abstract: A package includes a chip that has a metal-insulator-metal (MIM) capacitor formed in a first polymer layer and a metallic pillar formed on the MIM capacitor. A molding compound surrounds the chip, a second polymer layer is formed on the chip and the molding compound, a third polymer layer is formed on the second polymer layer, an interconnect structure is formed between the second polymer layer and the third polymer layer and electrically coupled to the metallic pillar and the MIM capacitor, and a bump is formed over and electrically coupled to the interconnect structure.

Abstract translation: 封装包括在第一聚合物层中形成的金属 - 绝缘体 - 金属（MIM）电容器和形成在MIM电容器上的金属柱的芯片。 模塑料包围芯片，在芯片和模塑料上形成第二聚合物层，在第二聚合物层上形成第三聚合物层，在第二聚合物层和第三聚合物层之间形成互连结构， 耦合到金属柱和MIM电容器，并且凸块形成在互连结构上并电耦合到互连结构。

公开(公告)号：US20250140667A1

公开(公告)日：2025-05-01

申请号：US18590271

申请日：2024-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chiang Chang ,  Hua-Wei Tseng ,  Ta-Hsuan Lin ,  Wei-Cheng Wu ,  Der-Chyang Yeh

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: In a semiconductor package having a redistribution structure, two or more semiconductor dies are connected to a first side of the redistribution structure and an encapsulant surrounds the two or more semiconductor dies. An integrated passive device (IPD) is connected on a second side of the redistribution structure. The second side is opposite to the first side and the IPD is electrically coupled to the redistribution structure. An interconnect device is connected on the second side of the redistribution structure and is electrically coupled to the redistribution structure. Two or more external connections are on the second side of the redistribution structure and are electrically coupled to the redistribution structure.

公开(公告)号：US12170207B2

公开(公告)日：2024-12-17

申请号：US18447460

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Der-Chyang Yeh ,  Li-Hsien Huang

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L25/10

Abstract: Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.