公开(公告)号：US07064360B2

公开(公告)日：2006-06-20

申请号：US10470816

申请日：2002-02-04

Applicant: Martin Franosch ,  Thomas Meister ,  Herbert Schaefer ,  Reinhard Stengl

Inventor： Martin Franosch ,  Thomas Meister ,  Herbert Schaefer ,  Reinhard Stengl

IPC: H01L31/0328

CPC classification number: H01L29/66242 ,  H01L29/7378

Abstract: A method is provided to fabricate a bipolar transistor with a low base connection resistance, low defect density and improved scalability. Scalability is to be understood in this case as both the lateral scaling of the emitter window and the vertical scaling of the base width (low temperature budget). The temperature budget can be kept low in the base region since no implantations are required in order to reduce the base connection resistance. Furthermore, the difficulties associated with the point defects are largely avoided.

Abstract translation: 提供了一种制造具有低基极连接电阻，低缺陷密度和改进的可扩展性的双极晶体管的方法。 在这种情况下可以理解可扩展性，因为发射器窗口的横向缩放和基础宽度（低温预算）的垂直缩放。 由于不需要植入来降低基极连接电阻，所以在基极区域中的温度预算可以保持较低。 此外，很大程度上避免了与点缺陷相关的困难。

公开(公告)号：US20060040456A1

公开(公告)日：2006-02-23

申请号：US11240297

申请日：2005-09-30

Applicant: Josef Bock ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer

Inventor： Josef Bock ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer

IPC: H01L21/331

CPC classification number: H01L29/66287 ,  H01L29/0649 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: The invention relates to a method for producing a bipolar semiconductor element, especially a bipolar transistor, and a corresponding bipolar semiconductor component. The inventive method comprises the following steps: a first semiconductor area (32, 34) of a first conductivity type (p) is provided above a semiconductor substrate (1); a connecting area (40) of the first conductivity type (p ) is provided above the semiconductor area (32, 34); a first insulating area (35″) is provided above the connecting area (40); a window (F) is formed within the first insulating area (35″) and the connecting area (40) so as to at least partly expose the semiconductor area (32, 34); a sidewall spacer (80) is provided in the window (F) in order to insulate the connecting area (40); a second semiconductor area (60) of the second conductivity type (n+) is provided so as to cover the sidewall spacer (80) and a portion of the surrounding first insulating area (35″); the surrounding first insulating area (35″) and the sidewall spacer (80) are removed in order to form a gap (LS) between the connecting area (40) and the second semiconductor area (60); and the gap (LS) is sealed by means of a second insulating area (100) while a gaseous atmosphere or a vacuum atmosphere is provided inside the sealed gap (LS).

Abstract translation: 本发明涉及一种用于制造双极型半导体元件，特别是双极晶体管的方法和相应的双极半导体元件。 本发明的方法包括以下步骤：第一导电类型（p）的第一半导体区域（32,34）设置在半导体衬底（1）的上方; 在半导体区域（32,34）的上方设置第一导电类型（p +）的连接区域（40）。 第一绝缘区域（35“）设置在连接区域40上方; 在第一绝缘区域（35“）和连接区域（40）内形成窗口（F），以便至少部分地暴露半导体区域（32,34）; 在窗口（F）中设置侧壁间隔件（80）以使连接区域（40）绝缘; 提供第二导电类型（n +）的第二半导体区域（60），以覆盖侧壁间隔物（80）和周围的第一绝缘区域（35“）的一部分; 为了在连接区域（40）和第二半导体区域（60）之间形成间隙（LS），除去周围的第一绝缘区域（35“）和侧壁间隔物（80） 并且在所述密封间隙（LS）的内部设置有气氛或真空气氛的同时，所述间隙（LS）借助于第二绝缘区域（100）密封。

公开(公告)号：US20060009002A1

公开(公告)日：2006-01-12

申请号：US10532894

申请日：2003-10-24

Applicant: Josef Bock ,  Rudolf Lachner ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer ,  Martin Seck

Inventor： Josef Bock ,  Rudolf Lachner ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer ,  Martin Seck

IPC: H01L21/331 ,  H01L21/8228

CPC classification number: H01L29/66272 ,  H01L21/8222 ,  H01L27/0825 ,  H01L29/0821

Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.

Abstract translation: 提出了一种制造具有不同集电极宽度的第一和第二双极晶体管的晶体管结构的方法。 该方法包括提供半导体衬底，将第一双极晶体管的第一掩埋层和第二双极晶体管的第二掩埋层引入到半导体衬底中，并且至少在第一掩埋层上产生具有第一集电极宽度的第一集电极区域 层和在第二掩埋层上具有第二集电极宽度的第二集电极区。 在第二掩埋层上产生具有第一厚度的第一收集器区，用于产生第二收集器宽度。 在第一收集器区域上产生具有第二厚度的第二收集器区域。 产生至少一个绝缘区域，其至少隔离收集器区域彼此。

公开(公告)号：US06635545B2

公开(公告)日：2003-10-21

申请号：US10160630

申请日：2002-06-03

Applicant: Josef Böck ,  Wolfgang Klein ,  Herbert Schäfer ,  Martin Franosch ,  Thomas Meister ,  Reinhard Stengl

Inventor： Josef Böck ,  Wolfgang Klein ,  Herbert Schäfer ,  Martin Franosch ,  Thomas Meister ,  Reinhard Stengl

IPC: H01L21331

CPC classification number: H01L29/66287 ,  H01L29/66242

Abstract: The bipolar transistor is produced such that a connection region of its base is provided with a silicide layer, so that a base resistance of the bipolar transistor is small. No silicide layer is produced between an emitter and an emitter contact and between a connection region of a collector and a collector contact. The base is produced by in situ-doped epitaxy in a region in which a first insulating layer is removed by isotropic etching such that the connection region of the base which is arranged on the first insulating layer is undercut. In order to avoid defects of a substrate in which the bipolar transistor is partly produced, isotropic etching is used for the patterning of auxiliary layers, whereby etching is selective with respect to auxiliary layers lying above, which are patterned by anisotropic etching.

公开(公告)号：US5326718A

公开(公告)日：1994-07-05

申请号：US950068

申请日：1992-09-23

Applicant: Helmut Klose ,  Thomas Meister ,  Hans-Willi Meul ,  Reinhard Stengl

Inventor： Helmut Klose ,  Thomas Meister ,  Hans-Willi Meul ,  Reinhard Stengl

IPC: H01L21/76 ,  H01L21/20 ,  H01L21/331 ,  H01L21/336 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78

CPC classification number: H01L29/66287 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02639 ,  H01L29/66651 ,  Y10S148/011

Abstract: A method for the manufacture of a laterally limited single crystal region that is suitable for use as an active part of a transistor.

Abstract translation: 一种用于制造适合用作晶体管的有源部分的横向受限的单晶区域的方法。

公开(公告)号：US20090011556A9

公开(公告)日：2009-01-08

申请号：US09948010

申请日：2001-09-05

Applicant: Gerhard Beitel ,  Wolfgang Hoenlein ,  Reinhard Stengl ,  Elke Fritsch ,  Siegfried Schwarzl ,  Hermann Wendt

Inventor： Gerhard Beitel ,  Wolfgang Hoenlein ,  Reinhard Stengl ,  Elke Fritsch ,  Siegfried Schwarzl ,  Hermann Wendt

IPC: H01L21/00 ,  H01L21/8242

CPC classification number: H01L28/60 ,  H01L21/02071 ,  H01L21/32136 ,  H01L28/55

Abstract: A method for producing a microelectronic structure is suggested in which a layer structure (30) which partially covers a substrate (5) and which comprises at least one first conductive layer (15,20) which reaches to a side wall (35) of the layer structure (30), is covered with a second conductive layer (45). The second conductive layer (45) is then subsequently back-etched to as great an extent as possible with an etching process with physical delamination, wherein delaminated material deposits on the side wall (35) of the layer structure (30). On the side wall (35) the delaminated material forms a protection layer (60) by means of which the first conductive layer (15,20) is to be protected from attack by oxygen to the furthest extent possible.

公开(公告)号：US06995416B2

公开(公告)日：2006-02-07

申请号：US10853734

申请日：2004-05-26

Applicant: Hans Reisinger ,  Reinhard Stengl ,  Herbert Schäfer

Inventor： Hans Reisinger ,  Reinhard Stengl ,  Herbert Schäfer

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C13/0033 ,  H01L27/10814 ,  H01L27/10852 ,  H01L28/91 ,  H01L51/0048 ,  H01L51/0052 ,  Y10S977/842 ,  Y10S977/943

Abstract: The invention provides a memory device for storing electrical charge, which has, as memory elements, tube elements applied on an electrode layer and connect-connected thereto. The tube elements are provided with a dielectric coating, a filling material for filling the space between the tube elements being provided. A counter-electrode connected to the filling material is formed such that an electrical capacitor for storing electrical charge is formed between the electrode layer and the counter-electrode. The tube elements advantageously comprise carbon nanotubes, as a result of which the capacitance of the capacitor on account of a drastic increase in the area of the capacitor electrode surface.

Abstract translation: 本发明提供一种用于存储电荷的存储装置，其具有作为存储元件的施加在电极层上并连接到其上的管元件。 管元件设置有电介质涂层，用于填充管元件之间的空间的填充材料。 与填充材料连接的对电极形成为在电极层和对电极之间形成用于存储电荷的电容器。 管元件有利地包括碳纳米管，结果由于电容器电极表面的面积急剧增加，电容器的电容。

公开(公告)号：US6165835A

公开(公告)日：2000-12-26

申请号：US341937

申请日：1999-07-20

Applicant: Hermann Wendt ,  Hans Reisinger ,  Andreas Spitzer ,  Reinhard Stengl ,  Ulrike Gruning ,  Josef Willer ,  Wolfgang Honlein ,  Volker Lehmann

Inventor： Hermann Wendt ,  Hans Reisinger ,  Andreas Spitzer ,  Reinhard Stengl ,  Ulrike Gruning ,  Josef Willer ,  Wolfgang Honlein ,  Volker Lehmann

IPC: H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L29/94

CPC classification number: H01L27/10861 ,  H01L29/66181 ,  Y10S438/96

Abstract: In producing a silicon capacitor, hole structures (2) are created in a silicon substrate (1), at the surface of which structures a conductive zone (3) is created by doping and whose surface is provided with a dielectric layer (4) and a conductive layer (5), without filling the hole structures (2). To compensate mechanical strains upon the silicon substrate (1) which are effected by the doping of the conductive zone (3), a conformal auxiliary layer (6) is formed on the surface of the conductive layer (5), which auxiliary layer is under a compressive mechanical stress.

Abstract translation: PCT No.PCT / DE98 / 00089 Sec。 371日期1999年7月20日 102（e）1999年7月20日PCT 1998年1月12日PCT PCT。 出版物WO98 / 32166 日期1998年7月23日在制造硅电容器中，在硅衬底（1）中形成孔结构（2），其表面通过掺杂形成导电区（3），并且其表面设置有电介质 层（4）和导电层（5），而不填充孔结构（2）。 为了补偿通过掺杂导电区（3）实现的硅衬底（1）上的机械应变，在导电层（5）的表面上形成共形辅助层（6），该辅助层在下面 压缩机械应力。

公开(公告)号：US5973385A

公开(公告)日：1999-10-26

申请号：US736301

申请日：1996-10-24

Applicant: Jeffrey Peter Gambino ,  Son Van Nguyen ,  Reinhard Stengl

Inventor： Jeffrey Peter Gambino ,  Son Van Nguyen ,  Reinhard Stengl

IPC: H01L21/28 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/58

CPC classification number: H01L21/02164 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/76801 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10T428/24926

Abstract: Significant amounts of pattern distortion were found to be the result of reflowing borophosphosilicate glass (BPSG) and silicon dioxide shrinkage during high temperature junction anneals. In order to remedy this problem, a method for suppressing the pattern distortion by subjecting the wafer coated with BPSG and with silicon dioxide layers to a high temperature anneal before patterning is disclosed. The high temperature anneal densifies the undoped silicon dioxide before patterning, so that shrinkage of the undoped silicon dioxide does not affect the patterning steps.

公开(公告)号：US5827765A

公开(公告)日：1998-10-27

申请号：US605622

申请日：1996-02-22

Applicant: Reinhard Stengl ,  Erwin Hammerl ,  Herbert L. Ho ,  Jack A. Mandelman ,  Radhika Srinivasan ,  Alvin P. Short

Inventor： Reinhard Stengl ,  Erwin Hammerl ,  Herbert L. Ho ,  Jack A. Mandelman ,  Radhika Srinivasan ,  Alvin P. Short

IPC: H01L27/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L21/20

CPC classification number: H01L27/10861 ,  H01L27/10832

Abstract: A method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell. The electrical connection is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.

Abstract translation: 一种用于在DRAM单元中的沟槽存储电容器和存取晶体管之间进行电连接的方法。 电连接是通过选择性地控制存在于沟槽中的N型或P型掺杂剂的扩散形成的，该单晶通过从沟槽侧壁外延（epi）生长的单晶半导体材料。 该外延生长的单晶层作为在常规DRAM的处理中可能发生的过量掺杂剂扩散扩散的障碍。