公开(公告)号：US09093565B2

公开(公告)日：2015-07-28

申请号：US13941555

申请日：2013-07-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L21/70 ,  H01L29/861 ,  H01L21/76 ,  H01L27/02

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/76 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/785 ,  H01L29/861

Abstract: A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type.

Abstract translation: 在本发明中提供了一种鳍式二极管结构及其制造方法，其结构包括：衬底，在衬底中形成的掺杂阱，多个第一导电类型的鳍和多个第二导电类型的鳍从 掺杂阱以及在第一导电类型的散热片，第二导电类型的散热片，浅沟槽隔离和掺杂阱之间的基板中全局形成的第一导电类型的掺杂区域，并与第一掺杂型的鳍片连接，以及 第二掺杂型散热片。

公开(公告)号：US20150014809A1

公开(公告)日：2015-01-15

申请号：US13941555

申请日：2013-07-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L29/861 ,  H01L21/76

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/76 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/785 ,  H01L29/861

Abstract: A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type.

Abstract translation: 在本发明中提供了一种鳍式二极管结构及其制造方法，其结构包括：衬底，在衬底中形成的掺杂阱，多个第一导电类型的鳍和多个第二导电类型的鳍从 掺杂阱以及在第一导电类型的散热片，第二导电类型的散热片，浅沟槽隔离和掺杂阱之间的基板中全局形成的第一导电类型的掺杂区域，并与第一掺杂型的鳍片连接，以及 第二掺杂型散热片。

公开(公告)号：US10903205B2

公开(公告)日：2021-01-26

申请号：US16394967

申请日：2019-04-25

Applicant: United Microelectronics Corp.

Inventor： Ting-Yao Lin ,  Chun Chiang ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/66

Abstract: A semiconductor device of ESD protection includes a first P-type well in a substrate to receive a protected terminal and a first N-type well abutting the first P-type well in the substrate. A second P-type well abutting the first N-type well is in the substrate. A second N-type well abutting the second P-type well is in the substrate. A detective circuit device is formed on a surface of the substrate, having an input terminal to receive the protected terminal and an output terminal to provide a trigger voltage to the first N-type well. A first route structure is in the substrate, on a sidewall and a bottom of the first P-type well to connect to a bottom of the first N-type well. A second route structure is in the substrate, on sidewall and bottom of the second N-type well, to connect to a bottom of the second P-type well.

公开(公告)号：US10522530B2

公开(公告)日：2019-12-31

申请号：US15927107

申请日：2018-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun Chiang ,  Ying-Wei Tseng ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L23/552 ,  H01L27/02 ,  H01L23/60 ,  G01R31/00 ,  G01R31/28 ,  H01L23/10

Abstract: An electrostatic discharge (ESD) shielding semiconductor device and an ESD testing method thereof, the ESD shielding semiconductor device includes an integrated circuit, a seal ring and a conductive layer. The integrated circuit is disposed on a die, and the integrated circuit has a first region and a second region. The seal ring is disposed on the die to surround the integrated circuit. The conductive layer at least covers the first region, and which is electrically connected to the seal ring.

公开(公告)号：US20180138167A1

公开(公告)日：2018-05-17

申请号：US15353348

申请日：2016-11-16

Applicant: United Microelectronics Corp.

Inventor： Chung-Yu Huang ,  Ping-Chen Chang ,  Hou-Jen Chiu

IPC: H01L27/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L27/0285 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66575

Abstract: An electrostatic discharge (ESD) device includes a gate structure, disposed on a substrate. A drain doped region of a first conductive type is in the substrate, adjacent to a first side of the gate structure, wherein the drain doped region has a first impurity concentration. A first doped region of the first conductive type is disposed within the drain doped region and being at least distant from the gate structure by a distance. The first doped region has a second impurity concentration lower than the first impurity concentration.

公开(公告)号：US09899369B2

公开(公告)日：2018-02-20

申请号：US14860788

申请日：2015-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pei-Shan Tseng ,  Yu-Cheng Liao ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L27/12

CPC classification number: H01L27/0266 ,  H01L27/0207 ,  H01L27/0255 ,  H01L27/1203 ,  H01L28/00

Abstract: A layout structure is provided. The layout structure includes a substrate, a gate conductive layer, a first doped region having a first conductivity, a second doped region having the first conductivity, and a third doped region having a second conductivity. The gate conductive layer is formed on the substrate. The first doped region the second doped region are formed in the substrate and located at two sides of the gate conductive layer. The third doped region is formed in the substrate and adjacent to the second doped region. The third doped region and the second doped region form a diode. The gate conductive layer, the first doped region, and the third doped region are connected to ground, and the second doped region is connected to an input/output pad.

公开(公告)号：US20160351558A1

公开(公告)日：2016-12-01

申请号：US15144836

申请日：2016-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chen ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L27/088 ,  H01L29/417

CPC classification number: H01L27/0266 ,  H01L27/0248 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/7851

Abstract: A fin type ESD protection device includes at least one first fin, at least one second fin, and at least one gate structure. The first fin is disposed on a semiconductor substrate, and a source contact contacts the first fin. The second fin is disposed on the semiconductor substrate, and a drain contact contacts the second fin. The first fin and the second fin extend in a first direction respectively, and the first fin is separated from the second fin. The gate structure is disposed between the source contact and the drain contact. The first fin is separated from the drain contact, and the second fin is separated from the source contact.

Abstract translation: 翅片型ESD保护装置包括至少一个第一鳍片，至少一个第二鳍片和至少一个栅极结构。 第一翅片设置在半导体衬底上，源极触点接触第一鳍片。 第二鳍片设置在半导体衬底上，漏极接触件接触第二鳍片。 第一鳍片和第二鳍片分别在第一方向上延伸，并且第一鳍片与第二鳍片分离。 栅极结构设置在源极触点和漏极触点之间。 第一鳍片与漏极接触部分开，第二鳍片与源极接触部分离开。

公开(公告)号：US09466598B1

公开(公告)日：2016-10-11

申请号：US14798564

申请日：2015-07-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Liao ,  Yu-Chun Chen ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/861

CPC classification number: H01L27/0255 ,  H01L27/0259 ,  H01L27/0262 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/861 ,  H01L29/87

Abstract: A semiconductor structure suitable for ESD protection application is provided. The semiconductor structure includes a first well, a second well, a third well, a first fin, a second fin, an anode, a cathode and a first doping region. The first well and the second well are disposed in the third well. The first fin is disposed on the first well. The second fin is disposed on the second well. The anode is disposed on the first fin. The cathode is disposed on the second fin. The first doping region is disposed under the first fin, and separates the first fin from the first well. The first well, the second well, the first fin and the second fin have a first doping type. The third well and the first doping region have a second doping type.

Abstract translation: 提供了适用于ESD保护应用的半导体结构。 半导体结构包括第一阱，第二阱，第三阱，第一鳍片，第二鳍片，阳极，阴极和第一掺杂区域。 第一口井和第二口井位于第三口井。 第一个翅片放在第一个井上。 第二个翅片设置在第二个孔上。 阳极设置在第一翅片上。 阴极设置在第二散热片上。 第一掺杂区域设置在第一鳍片下方，并且将第一鳍片与第一阱分离。 第一井，第二井，第一鳍和第二鳍具有第一种掺杂类型。 第三阱和第一掺杂区具有第二掺杂类型。

公开(公告)号：US09455246B2

公开(公告)日：2016-09-27

申请号：US14687921

申请日：2015-04-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L21/70 ,  H01L27/02 ,  H01L29/861 ,  H01L21/76 ,  H01L29/78 ,  H01L27/06 ,  H01L29/06 ,  H01L21/22 ,  H01L21/265 ,  H01L21/306 ,  H01L29/66 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/76 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/785 ,  H01L29/861

Abstract: A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type.

公开(公告)号：US20160260700A1

公开(公告)日：2016-09-08

申请号：US14724825

申请日：2015-05-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Chen Chang

IPC: H01L27/02 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L27/0255 ,  H01L27/027 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/78 ,  H01L29/7818 ,  H01L29/7831 ,  H01L29/7835

Abstract: An electrostatic discharge protection semiconductor device includes a substrate, a gate set positioned on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, at least a first doped region formed in the drain region, and at least a second doped region formed in the substrate. The source region and the drain region include a first conductivity type, the first doped region and the second doped region include a second conductivity type, and the first conductivity and the second conductivity type are complementary to each other. The first doped region and the second doped region are electrically connected to each other.

Abstract translation: 一种静电放电保护半导体器件，包括：基板，位于基板上的栅极集电体，分别位于栅极集合体两侧的基板上形成的源极区域和漏极区域，形成在漏极区域中的至少第一掺杂区域， 以及形成在所述衬底中的至少第二掺杂区域。 源极区域和漏极区域包括第一导电类型，第一掺杂区域和第二掺杂区域包括第二导电类型，并且第一导电性和第二导电类型彼此互补。 第一掺杂区域和第二掺杂区域彼此电连接。