公开(公告)号：US10366978B1

公开(公告)日：2019-07-30

申请号：US16036914

申请日：2018-07-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Hsiang Chang ,  Hou-Jen Chiu ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08

Abstract: A grounded gate NMOS transistor includes a P-type substrate, P-well region in the P-type substrate, and a gate finger traversing the P-well region. The gate finger has a first spacer on a first sidewall and a second spacer on a second sidewall opposite to the first sidewall. An N+ drain doping region is disposed in the P-type substrate and is adjacent to the first sidewall of the gate finger. The N+ drain doping region is contiguous with a bottom edge of the first spacer. An N+ source doping region is disposed in the P-type substrate opposite to the N+ drain doping region. The N+ source doping region is kept a predetermined distance from a bottom edge of the second spacer. A P+ pick-up ring is disposed in the P-well region and surrounds the gate finger, the N+ drain doping region, and the N+ source doping region.

公开(公告)号：US20190006348A1

公开(公告)日：2019-01-03

申请号：US16124171

申请日：2018-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Jui Chen ,  Po-Ya Lai

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10

Abstract: An ESD protection semiconductor device is disclosed. The ESD protection semiconductor device includes a substrate and a gate set disposed on the substrate. A plurality of source fins and a plurality of drain fins are formed in the substrate respectively at two sides of the gate set. At least a first doped fin is formed in the substrate at one side of the gate set the same as the source fins. A plurality of isolation structures are formed in one of the drain fins to define at least a second doped fin in the one of the drain fins. The source fins and the drain fins are of a first conductivity type. The first doped fin is of a second conductivity type that is complementary to the first conductivity type. The first doped fin and the second doped fin are electrically connected to each other.

公开(公告)号：US20170309613A1

公开(公告)日：2017-10-26

申请号：US15138226

申请日：2016-04-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L29/417 ,  H01L27/092

CPC classification number: H01L27/0277 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0262 ,  H01L27/027 ,  H01L27/0274 ,  H01L29/0619 ,  H01L29/0626 ,  H01L29/0692 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/41725 ,  H01L29/735

Abstract: A layout structure of an ESD protection semiconductor device includes a substrate, a first doped region, a pair of second doped regions, a pair of third doped regions, at least a first gate structure formed within the first doped region, and a drain region and a first source region formed at two sides of the first gate structure. The substrate, the first doped region and the third doped regions include a first conductivity type. The second doped regions, the drain region and the first source region include a second conductivity type complementary to the first conductivity type. The first doped region includes a pair of lateral portions and a pair of vertical portions. The pair of second doped regions is formed under the pair of lateral portions, and the pair of third doped regions is formed under the pair of vertical portions.

公开(公告)号：US09607977B1

公开(公告)日：2017-03-28

申请号：US14920902

申请日：2015-10-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Cih Wang ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8249 ,  H01L21/8234

CPC classification number: H01L21/823475 ,  H01L21/8249 ,  H01L27/027 ,  H01L29/1095 ,  H01L29/78 ,  H01L29/7816

Abstract: An electrostatic discharge protection device includes an anode, a cathode, a negative voltage holding transistor and a positive voltage holding transistor. The anode is coupled to an input terminal, and the cathode is coupled to a ground. The negative voltage holding transistor includes an N-well. The positive voltage holding transistor includes an N-well. The N-well of the positive voltage holding transistor and the N-well of the negative voltage holding transistor are coupled together and are float. The negative voltage holding transistor and the positive voltage holding transistor are coupled between the anode and the cathode in a manner of back-to-back.

公开(公告)号：US20170084604A1

公开(公告)日：2017-03-23

申请号：US14860788

申请日：2015-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pei-Shan Tseng ,  Yu-Cheng Liao ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02

CPC classification number: H01L27/0266 ,  H01L27/0207 ,  H01L27/0255 ,  H01L27/1203 ,  H01L28/00

Abstract: A layout structure is provided. The layout structure includes a substrate, a gate conductive layer, a first doped region having a first conductivity, a second doped region having the first conductivity, and a third doped region having a second conductivity. The gate conductive layer is formed on the substrate. The first doped region the second doped region are formed in the substrate and located at two sides of the gate conductive layer. The third doped region is formed in the substrate and adjacent to the second doped region. The third doped region and the second doped region form a diode. The gate conductive layer, the first doped region, and the third doped region are connected to ground, and the second doped region is connected to an input/output pad.

公开(公告)号：US09564436B2

公开(公告)日：2017-02-07

申请号：US14082529

申请日：2013-11-18

Applicant: United Microelectronics Corp.

Inventor： Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H02H9/04 ,  H01L27/092 ,  H01L27/02 ,  H01L27/088

CPC classification number: H01L27/092 ,  H01L27/0277 ,  H01L27/088

Abstract: A semiconductor device is described, including a substrate including a first area and a second area, a first MOS element of a first conductivity type in the first area, and a second MOS element of the first conductivity type in the second area. The first area is closer to a pick-up region of the substrate than the second area. The substrate has a second conductivity type. The bottom depth of a first electrical conduction path in the substrate in the first area is smaller than that of a second electrical conduction path in the substrate in the second area.

Abstract translation: 描述了一种半导体器件，包括包括第一区域和第二区域的衬底，第一区域中的第一导电类型的第一MOS元件和第二区域中的第一导电类型的第二MOS元件。 第一区域比第二区域更靠近基板的拾取区域。 衬底具有第二导电类型。 第一区域中的衬底中的第一导电通路的底部深度小于第二区域中的衬底中的第二导电通路的深度。

公开(公告)号：US09559091B2

公开(公告)日：2017-01-31

申请号：US14745458

申请日：2015-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L21/70 ,  H01L27/02 ,  H01L29/861 ,  H01L21/76 ,  H01L29/78 ,  H01L27/06 ,  H01L29/06 ,  H01L21/22 ,  H01L21/265 ,  H01L21/306 ,  H01L29/66 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/76 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/785 ,  H01L29/861

Abstract: A method of manufacturing a fin diode structure includes providing a substrate, forming a doped well in said substrate, forming at least one doped region of first conductivity type or at least one doped region of second doped type in said doped well, performing an etching process to said doped region of first conductivity type or said doped region of second conductivity type to form a plurality of fins on said doped region of first conductivity type or on said doped region of second conductivity type, forming shallow trench isolations between said fins, and performing a doping process to said fins to form fins of first conductivity type and fins of second conductivity type.

Abstract translation: 制造鳍式二极管结构的方法包括提供衬底，在所述衬底中形成掺杂阱，在所述掺杂阱中形成至少一个第一导电类型的掺杂区或第二掺杂型的至少一个掺杂区，执行蚀刻工艺 到所述第一导电类型的掺杂区域或第二导电类型的所述掺杂区域，以在所述第一导电类型的掺杂区域上或在所述第二导电类型的所述掺杂区域上形成多个鳍片，在所述鳍片之间形成浅沟槽隔离，并执行 对所述翅片进行掺杂工艺以形成第一导电类型的鳍片和第二导电类型的鳍片。

公开(公告)号：US09331161B1

公开(公告)日：2016-05-03

申请号：US14554068

申请日：2014-11-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Ju Lee ,  Yao-Chang Wang ,  Nien-Ting Ho ,  Chi-Mao Hsu ,  Kuan-Cheng Su ,  Main-Gwo Chen ,  Hsiao-Kwang Yang ,  Fang-Hong Yao ,  Sheng-Huei Dai ,  Tzung-Lin Li

IPC: H01L21/02 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L29/42376 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02194 ,  H01L21/02244 ,  H01L21/02255 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/78

Abstract: The present invention provides a metal gate structure which is formed in a trench of a dielectric layer. The metal gate structure includes a work function metal layer and a metal layer. The work function metal layer is disposed in the trench and comprises a bottom portion and a side portion, wherein a ratio between a thickness of the bottom portion and a thickness of the side portion is between 2 and 5. The trench is filled with the metal layer. The present invention further provides a method of forming the metal gate structure.

Abstract translation: 本发明提供了形成在电介质层的沟槽中的金属栅极结构。 金属栅极结构包括功函数金属层和金属层。 工作功能金属层设置在沟槽中，并且包括底部和侧部，其中底部的厚度和侧部的厚度之间的比率在2-5之间。沟槽填充有金属 层。 本发明还提供一种形成金属栅极结构的方法。

公开(公告)号：US20150303183A1

公开(公告)日：2015-10-22

申请号：US14745458

申请日：2015-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L21/76 ,  H01L21/22 ,  H01L21/265 ,  H01L29/06 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/76 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/785 ,  H01L29/861

Abstract: A method of manufacturing a fin diode structure includes providing a substrate, forming a doped well in said substrate, forming at least one doped region of first conductivity type or at least one doped region of second doped type in said doped well, performing an etching process to said doped region of first conductivity type or said doped region of second conductivity type to form a plurality of fins on said doped region of first conductivity type or on said doped region of second conductivity type, forming shallow trench isolations between said fins, and performing a doping process to said fins to form fins of first conductivity type and fins of second conductivity type.

Abstract translation: 制造鳍式二极管结构的方法包括提供衬底，在所述衬底中形成掺杂阱，在所述掺杂阱中形成至少一个第一导电类型的掺杂区或第二掺杂型的至少一个掺杂区，执行蚀刻工艺 到所述第一导电类型的掺杂区域或第二导电类型的所述掺杂区域，以在所述第一导电类型的掺杂区域上或在所述第二导电类型的所述掺杂区域上形成多个鳍片，在所述鳍片之间形成浅沟槽隔离，并执行 对所述翅片进行掺杂工艺以形成第一导电类型的鳍片和第二导电类型的鳍片。

公开(公告)号：US20150221632A1

公开(公告)日：2015-08-06

申请号：US14687921

申请日：2015-04-16

Applicant: United Microelectronics Corp.

Inventor： Chang-Tzu Wang ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L29/78 ,  H01L27/06 ,  H01L29/861 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/76 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/785 ,  H01L29/861

Abstract: A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type.