公开(公告)号：US10141398B1

公开(公告)日：2018-11-27

申请号：US15844942

申请日：2017-12-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Tsai ,  Jung Han ,  Chin-Chia Kuo ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L27/118 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L21/28 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49

Abstract: A semiconductor structure includes a HV NMOS structure. The HV NMOS structure includes a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. The source region and the drain region are separated from each other. The channel region is disposed between the source region and the drain region. The channel region has a channel direction from the source region toward the drain region. The gate dielectric is disposed on the channel region and on portions of the source region and the drain region. The gate electrode is disposed on the gate dielectric. The gate electrode includes a first portion of n-type doping and two second portions of p-type doping. The two second portions are disposed at two sides of the first portion. The two second portions have an extending direction perpendicular to the channel direction.

公开(公告)号：US20180102408A1

公开(公告)日：2018-04-12

申请号：US15287535

申请日：2016-10-06

Applicant: United Microelectronics Corp.

Inventor： Chang-Po Hsiung ,  Ping-Hung Chiang ,  Shih-Chieh Pu ,  Chia-Lin Wang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Shih-Yin Hsiao ,  Chih-Chung Wang

IPC: H01L29/06 ,  H01L29/51 ,  H01L21/762 ,  H01L21/311 ,  H01L27/088

CPC classification number: H01L29/0649 ,  H01L21/31111 ,  H01L21/7621 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517

Abstract: A method of forming a semiconductor device is provided including the following steps. A substrate having a first voltage area and a second voltage area is provided. A first oxide layer is formed in the first voltage area. The first oxide layer is removed to form a recess in the first voltage area. A shallow trench isolation (STI) structure is formed in the substrate, wherein a first portion of the STI structure is located in the first voltage area and a second portion of the STI structure is located in the second voltage area, a top surface of the STI structure is higher than the top surface of the substrate, and a bottom surface of the first portion of the STI structure in the first voltage area is lower than a bottom surface of the second portion of the STI structure in the second voltage area.

公开(公告)号：US20170330947A1

公开(公告)日：2017-11-16

申请号：US15667633

申请日：2017-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Wen-Fang Lee ,  Nien-Chung Li ,  Chih-Chung Wang

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L23/535 ,  G06F17/50

CPC classification number: H01L29/4238 ,  G06F17/5072 ,  H01L23/535 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/4983 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/7836 ,  H01L29/785

Abstract: A metal-oxide semiconductor transistor includes a substrate, a gate insulating layer disposed on a surface of the substrate, and a metal gate disposed on the gate insulating layer, wherein at least one of the length or the width of the metal gate is greater than or equal to approximately 320 nanometers, and the metal gate has at least one plug hole. The metal-oxide semiconductor transistor further includes at least one insulating plug disposed in the plug hole and two diffusion regions disposed respectively at two sides of the metal gate in the substrate.

公开(公告)号：US09716139B2

公开(公告)日：2017-07-25

申请号：US14727875

申请日：2015-06-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Chuan Chen ,  Chih-Chung Wang ,  Wen-Fang Lee ,  Nien-Chung Li ,  Shih-Yin Hsiao

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/0653 ,  H01L21/28238 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/66613

Abstract: A method for forming a high voltage transistor is provided. First, a substrate having a top surface is provided, following by forming a thermal oxide layer on the substrate. At least a part of the thermal oxidation layer is removed to form a recess in the substrate, wherein a bottom surface of the recess is lower than the top surface of the substrate. A gate oxide layer is formed in the recess, then a gate structure is formed on the gate oxide layer. The method further includes forming a source/drain region in the substrate.

公开(公告)号：US09653460B1

公开(公告)日：2017-05-16

申请号：US15057130

申请日：2016-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li ,  Kuan-Chuan Chen ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L27/088 ,  H01L29/49 ,  H01L27/02 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/45 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L21/823456 ,  H01L21/28035 ,  H01L21/28088 ,  H01L21/31051 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a first gate and a second gate. The first gate is disposed on the substrate and includes a first gate insulating layer, a polysilicon layer, a silicide layer and a protective layer stacked with each other on the substrate and a first spacer surrounds the first gate insulating layer, the polysilicon layer, the silicide layer and the protective layer. The second gate is disposed on the substrate and includes a second gate insulating layer, a work function metal layer and a conductive layer stacked with each other on the substrate, and a second spacer surrounds the second gate insulating layer, the work function metal layer and the conductive layer.

公开(公告)号：US09484422B2

公开(公告)日：2016-11-01

申请号：US14882462

申请日：2015-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao ,  Wen-Fang Lee ,  Shu-Wen Lin ,  Kuan-Chuan Chen

IPC: H01L29/76 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/08 ,  H01L21/266 ,  H01L21/28 ,  H01L21/265

CPC classification number: H01L29/42368 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28026 ,  H01L21/28158 ,  H01L21/2822 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/401 ,  H01L29/6659 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7834

Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.

Abstract translation: 本发明提供一种高压金属氧化物半导体（HVMOS）晶体管，其包括衬底，栅极电介质层，栅极电极和源极和漏极区域。 栅介质层设置在基板上，并且包括突出部分和凹陷部分，其中突出部分邻近凹部的两侧设置，并且具有大于凹部的厚度的厚度。 栅电极设置在栅介质层上。 因此，栅极电介质层的突出部分可以保持更高的击穿电压，从而保持电流不通过栅极泄漏。

公开(公告)号：US20160043193A1

公开(公告)日：2016-02-11

申请号：US14882462

申请日：2015-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao ,  Wen-Fang Lee ,  Shu-Wen Lin ,  Kuan-Chuan Chen

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/42368 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28026 ,  H01L21/28158 ,  H01L21/2822 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/401 ,  H01L29/6659 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7834

Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.

Abstract translation: 本发明提供一种高压金属氧化物半导体（HVMOS）晶体管，其包括衬底，栅极电介质层，栅极电极和源极和漏极区域。 栅介质层设置在基板上，并且包括突出部分和凹陷部分，其中突出部分邻近凹部的两侧设置，并且具有大于凹部的厚度的厚度。 栅电极设置在栅介质层上。 因此，栅极电介质层的突出部分可以保持更高的击穿电压，从而保持电流不通过栅极泄漏。

公开(公告)号：US20150287797A1

公开(公告)日：2015-10-08

申请号：US14273538

申请日：2014-05-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao ,  Wen-Fang Lee ,  Shu-Wen Lin ,  Kuan-Chuan Chen

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/08 ,  H01L21/266 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/42368 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28026 ,  H01L21/28158 ,  H01L21/2822 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/401 ,  H01L29/6659 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7834

Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.

Abstract translation: 本发明提供一种高压金属氧化物半导体（HVMOS）晶体管，其包括衬底，栅极电介质层，栅极电极和源极和漏极区域。 栅介质层设置在基板上，并且包括突出部分和凹陷部分，其中突出部分邻近凹部的两侧设置，并且具有大于凹部的厚度的厚度。 栅电极设置在栅介质层上。 因此，栅极电介质层的突出部分可以保持更高的击穿电压，从而保持电流不通过栅极泄漏。

公开(公告)号：US20250048671A1

公开(公告)日：2025-02-06

申请号：US18459454

申请日：2023-09-01

Applicant: United Microelectronics Corp.

Inventor： Hsuan-Kai Chen ,  Tun-Jen Cheng ,  Ching-Chung Yang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chiu-Te Lee

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/423

Abstract: A transistor structure including a substrate, a gate dielectric layer, a gate, a first doped region, a second doped region, a first drift region, and a dummy gate is provided. The gate dielectric layer is located on the substrate. The gate dielectric layer includes first and second portions. The second portion is connected to the first portion. The thickness of the second portion is greater than the thickness of the first portion. The gate is located on the first and second portions. The first doped region and the second doped region are located in the substrate on two sides of the gate dielectric layer. The first drift region is located in the substrate on one side of the gate. The second doped region is located in the first drift region. The dummy gate is located on the second portion between the gate and the second doped region.

公开(公告)号：US20240429220A1

公开(公告)日：2024-12-26

申请号：US18224057

申请日：2023-07-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Te Lee ,  Wen-Fang Lee ,  Shan-Shi Huang ,  Kuan-Chuan Chen

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: The invention provides a semiconductor structure, which comprises a first silicon substrate with a display region and a driving region defined thereon, a circuit layer located on the first silicon substrate, a plurality of light emitting elements located on the display region of the first silicon substrate, a driving chip located on the driving region of the first silicon substrate and electrically connected with the circuit layer, and a second silicon substrate located on the driving chip.