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公开(公告)号：US11620500B2
公开(公告)日：2023-04-04
申请号：US15868392
申请日：2018-01-11
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Ping-Kun Wang , Shao-Ching Liao , Chih-Cheng Fu , Ming-Che Lin , Yu-Ting Chen , Seow-Fong (Dennis) Lim
Abstract: A synapse system is provided which includes three transistors and a resistance-switching element arranged between two neurons. The resistance-switching element has a resistance value and it is arranged between two neurons. A first transistor is connected between the resistance-switching element and one of the neurons. A second transistor and a third transistor are arranged between the two neurons, and are connected in series which interconnects with the gate of the first transistor. A first input signal is transmitted from one of the neurons to the other neuron through the first transistor. A second input signal is transmitted from one of the neurons to the other neuron through the second transistor and the third transistor. The resistance value of the resistance-switching element is changed based on the time difference between the first input signal and the second input signal.
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公开(公告)号：US11520526B2
公开(公告)日：2022-12-06
申请号：US17337003
申请日：2021-06-02
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Shao-Ching Liao , Chien-Min Wu , Chia Hua Ho , Frederick Chen , He-Hsuan Chao , Seow-Fong Lim
Abstract: A write method for a resistive memory including a storage array, a control circuit and an access circuit is provided. The control circuit receives an external command to activate the access circuit to access the storage array. The write method includes determining whether the external command is ready to perform a write operation for the storage array; generating a first operation voltage group to the access circuit when the external command does not perform the write operation for the storage array; reading a count value of a block that corresponds to a write address when the external command performs the write operation for the storage array, wherein the count value indicates the number of times that the block corresponding to the write address performs the write operation; and generating a second operation voltage group to the access circuit according to the count value of the block.
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公开(公告)号：US11289541B2
公开(公告)日：2022-03-29
申请号：US16683467
申请日：2019-11-14
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen
IPC: H01L27/24 , H01L45/00 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/78 , H01L21/265 , H01L21/306 , H01L21/74 , H01L29/66
Abstract: A resistive random access memory (RRAM) device is provided. The RRAM device includes a gate structure on a substrate, and a source region and a drain region disposed on opposite sides of the gate structure on the substrate. The source region includes a semiconductor bulk, and the drain region includes a plurality of semiconductor fins adjacent to the semiconductor bulk, wherein the semiconductor fins are separated from each other by an isolation layer. The RRAM device further includes a plurality of RRAM units, wherein each of the RRAM units electrically contacts one of the semiconductor fins.
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公开(公告)号：US20220069209A1
公开(公告)日：2022-03-03
申请号：US17002759
申请日：2020-08-25
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Chia-Wen Cheng , He-Hsuan Chao , Frederick Chen , Chang-Tsung Pai , Tzu-Yun Huang , Ming-Che Lin
Abstract: A resistive memory device and a reliability enhancement method thereof are provided. The reliability enhancement method includes the following steps. A forming operation is performed on a plurality of memory cells. The formed memory cells are read to respectively obtain a plurality of formed currents. A reference current is set according to a statistic value of the formed currents. A setting operation is performed on the memory cells. A ratio between a set current of each of the memory cells and the reference current is calculated, and a physical status of each of the memory cells is judged according to the ratio. It is determined whether to perform a fix operation of each of the memory cells or not according to physical status.
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公开(公告)号：US10756264B2
公开(公告)日：2020-08-25
申请号：US16129764
申请日：2018-09-12
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen
Abstract: The resistance change memory device including a first resistance change memory element, a second resistance change memory element, and a memory controller is provided. The first resistance change memory element is disposed on a chip. The second resistance change memory element is disposed on the same chip. The memory controller is disposed on the same chip. The memory controller is configured to control data access of the first resistance change memory element and the second resistance change memory element. An accessing frequency of the first resistance change memory element is different from an accessing frequency of the second resistance change memory element.
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Patent Agency Ranking
公开(公告)号：US20180175289A1
公开(公告)日：2018-06-21
申请号：US15379505
申请日：2016-12-15
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen
CPC classification number: H01L45/06 , G11C11/005 , G11C13/0004 , G11C13/003 , G11C13/0035 , H01L27/2463 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1675
Abstract: The resistance change memory device including a first resistance change memory element, a second resistance change memory element, and a memory controller is provided. The first resistance change memory element is disposed on a chip. The second resistance change memory element is disposed on the same chip. The memory controller is disposed on the same chip. The memory controller is configured to control data access of the first resistance change memory element and the second resistance change memory element. An accessing frequency of the first resistance change memory element is different from an accessing frequency of the second resistance change memory element.
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公开(公告)号：US09734908B1
公开(公告)日：2017-08-15
申请号：US15076688
申请日：2016-03-22
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen
IPC: G11C13/00
CPC classification number: G11C13/0097 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2013/0073 , G11C2013/0092
Abstract: A writing method for a resistive memory cell and a resistive memory using thereof are provided. In the writing method, a group of RESET signals is provided to the resistive memory cell, so as to execute a writing operation. A current of the resistive memory cell is detected to determine whether the writing operation of the resistive memory cell is completed. When the writing operation of the resistive memory cell is not completed, widths of filament paths in the resistive memory cell are determined to be narrowed or not. The voltage of word line of the resistive memory cell in the group of RESET signals is reduced when the widths of the filament paths in the resistive memory cell are narrowed.
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公开(公告)号：US20170117038A1
公开(公告)日：2017-04-27
申请号：US14918574
申请日：2015-10-21
Applicant: Winbond Electronics Corp.
Inventor： Shao-Ching Liao , Ping-Kun Wang , Frederick Chen
IPC: G11C13/00
CPC classification number: G11C11/00 , G11C5/147 , G11C11/5642 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , H01L27/2409 , H01L45/00
Abstract: An operating method for a resistive memory cell and a resistive memory are provided. The operating method for the resistive memory cell includes following steps. A forming operation for the resistive memory cell is performed. Whether the resistive memory cell is in a first state is determined, wherein the first state is corresponding to a first operation. When the resistive memory cell is not in the first state, a complementary switching operation regarding a second operation for the resistive memory cell is performed, so that the resistive memory cell generates a complementary switching phenomenon regarding the second operation. Thus, the resistive memory cell which cannot retain data by normal forming operation can effectively obtain the data retention capability by the complementary switching phenomenon.
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公开(公告)号：US09496036B1
公开(公告)日：2016-11-15
申请号：US14953447
申请日：2015-11-30
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Ping-Kun Wang , Shao-Ching Liao , Pei-Hsiang Liao
CPC classification number: G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2013/009 , G11C2013/0092 , G11C2213/79 , G11C2213/82
Abstract: A writing method for a resistive memory cell and a resistive memory are provided. The writing method includes following steps. A reference voltage is provided to a bit line of the resistive memory cell. A first voltage is provided to a word line of the resistive memory cell, and a second voltage is provided to a source line of the resistive memory cell, wherein the first voltage is not increased while the second voltage is progressively increased. Thus, when the writing method for the resistive memory cell is performed, the voltage of the word line is not increased while the voltage of the source line is progressively increased, so as to expand voltage window for reset operation. And, the chance for occurring the complementary switching manifestation of the resistive memory cell due to excessive input voltages is reduced.
Abstract translation: 提供了一种用于电阻式存储单元和电阻式存储器的写入方法。 写作方法包括以下步骤。 参考电压被提供给电阻存储单元的位线。 第一电压被提供给电阻存储单元的字线，并且第二电压被提供给电阻存储单元的源极线，其中第一电压不增加，而第二电压逐渐增加。 因此，当执行电阻性存储单元的写入方法时，在线源的电压逐渐增加的同时，字线的电压不增加，从而扩大用于复位操作的电压窗口。 并且，由于过大的输入电压而发生电阻式存储单元的互补切换表现的机会降低。
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公开(公告)号：US20250072008A1
公开(公告)日：2025-02-27
申请号：US18939533
申请日：2024-11-07
Applicant: Winbond Electronics Corp.
Inventor： Chi-Ching Liu , Chih-Chao Huang , Ming-Che Lin , Frederick Chen , Han-Huei Hsu
Abstract: Provided is a semiconductor device including: a substrate, a plurality of isolation structures, a plurality of channel layers, and a gate structure. The substrate includes a plurality of fins thereon. The plurality of isolation structures are respectively disposed between the plurality of fins. A top surface of the plurality of isolation structures is higher than a top surface of the plurality of fins to form a plurality of openings. The plurality of channel layers are respectively disposed in the plurality of openings. Each channel layer is in contact with a corresponding fin and extends to cover a lower sidewall of a corresponding isolation structure, thereby forming a U-shaped structure. The gate structure is filled in the plurality of openings and extends to cover the top surface of the plurality of isolation structures.
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