公开(公告)号：US20190196901A1

公开(公告)日：2019-06-27

申请号：US15851449

申请日：2017-12-21

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  Ian A. Swarbrick ,  Sagheer Ahmad

IPC: G06F11/10 ,  G11C29/52 ,  G06F13/16 ,  G06F15/78

CPC classification number: G06F15/7825 ,  G06F11/10 ,  G06F11/1068 ,  G06F13/1668 ,  G11C29/52

Abstract: An example integrated circuit (IC) includes a network-on-chip (NoC), a master device coupled to the NoC, a memory controller coupled to the NoC configured to control a memory coupled to the IC, and an inline error-correcting code (ECC) circuit coupled to the NoC. The ECC circuit is configured to receive read and write transactions from the master device that target the memory, compute ECC data based on the read and write transactions, and provide outgoing transactions to the memory controller.

公开(公告)号：US20190050252A1

公开(公告)日：2019-02-14

申请号：US15673220

申请日：2017-08-09

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel

IPC: G06F9/46 ,  G06F13/16 ,  G06F15/78 ,  G06F3/06

CPC classification number: G06F9/467 ,  G06F3/061 ,  G06F3/0628 ,  G06F3/064 ,  G06F11/3027 ,  G06F11/349 ,  G06F13/1621 ,  G06F13/1668 ,  G06F15/7807

Abstract: Disclosed approaches of controlling quality of service in servicing memory transactions includes periodically reading by a quality of service management (QM) circuit, respective first data rate metrics and respective latency metrics from requester circuits while the requester circuits are actively transmitting memory transactions to a memory controller. The QM circuit periodically reads a second data rate metric from the memory controller while the memory controller is processing the memory transactions, and determines, while the requester circuits are actively transmitting memory transactions to the memory controller, whether or not the respective first data rate metrics, respective latency metrics, and second data rate metric satisfy a quality of service metric. In response to determining that the operating metrics do not satisfy the quality of service metric, the QM circuit dynamically changes value(s) of a control parameter(s) of the requester circuit(s) and of the memory controller.

公开(公告)号：US09213866B1

公开(公告)日：2015-12-15

申请号：US14242268

申请日：2014-04-01

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Ygal Arbel

IPC: G06F21/76 ,  G06F21/78

CPC classification number: G06F21/76

Abstract: A circuit for preventing unauthorized access in an integrated circuit includes a plurality of circuit block and a plurality of protection circuits. Each protection circuit is coupled to an input of a corresponding circuit block of the plurality of circuit blocks. Each protection circuit determines whether an access request to the corresponding circuit block is authorized. The protection circuits could be implemented to monitor system-on-chip interconnections of master and slave circuits, for example. A method of preventing unauthorized access in an integrated circuit could be implemented using the circuit.

Abstract translation: 用于防止集成电路中的未授权访问的电路包括多个电路块和多个保护电路。 每个保护电路耦合到多个电路块的相应电路块的输入端。 每个保护电路确定对相应电路块的访问请求是否被授权。 例如，可以实施保护电路来监视主电路和从电路的片上系统互连。 可以使用该电路来实现防止集成电路中的未授权访问的方法。

公开(公告)号：US09130559B1

公开(公告)日：2015-09-08

申请号：US14495024

申请日：2014-09-24

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Bradley L. Taylor ,  Ygal Arbel

IPC: H03K19/177 ,  H03K19/003 ,  H03K19/007 ,  G06F15/78

CPC classification number: H03K19/003 ,  G06F15/7867 ,  H03K19/007 ,  H03K19/177 ,  H03K19/17764 ,  H03K19/17768

Abstract: A programmable IC is disclosed that includes a programmable logic sub-system, a processing sub-system, and a safety sub-system. The programmable logic sub-system includes programmable logic circuits configured to form a hardware portion of a user design. The processing sub-system includes processing circuits configured to execute a software portion of a user design. The safety sub-system is configured to perform a safety functions that detect and/or mitigate errors in circuits of the programmable IC. The safety sub-system includes hard-wired circuits configured to perform hardware-based safety functions for a first subset of circuits of the programmable IC. The safety sub-system also includes a processing circuit configured to execute software-based safety functions for a second subset of circuits of the programmable IC.

Abstract translation: 公开了一种可编程IC，其包括可编程逻辑子系统，处理子系统和安全子系统。 可编程逻辑子系统包括被配置为形成用户设计的硬件部分的可编程逻辑电路。 处理子系统包括被配置为执行用户设计的软件部分的处理电路。 安全子系统被配置为执行检测和/或减轻可编程IC的电路中的错误的安全功能。 安全子系统包括被配置为对可编程IC的电路的第一子集执行基于硬件的安全功能的硬连线电路。 安全子系统还包括处理电路，其被配置为对可编程IC的电路的第二子集执行基于软件的安全功能。

公开(公告)号：US12237287B2

公开(公告)日：2025-02-25

申请号：US18369115

申请日：2023-09-15

Applicant: XILINX, INC.

Inventor： Ygal Arbel ,  Kenneth Ma ,  Balakrishna Jayadev ,  Sagheer Ahmad

IPC: G11C5/00 ,  G11C5/06 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

Abstract: Embodiments herein describe a multiple die system that includes an interposer that connects a first die to a second die. Each die has a bump interface structure that is connected to the other structure using traces in the interposer. However, the bump interface structures may have different orientations relative to each other, or one of the interface structures defines fewer signals than the other. Directly connecting the corresponding signals defined by the structures to each other may be impossible to do in the interposer, or make the interposer too costly. Instead, the embodiments here simplify routing in the interposer by connecting the signals in the bump interface structures in a way that simplifies the routing but jumbles the signals. The jumbled signals can then be corrected using reordering circuitry in the dies (e.g., in the link layer and physical layer).

公开(公告)号：US12045502B1

公开(公告)日：2024-07-23

申请号：US17356248

申请日：2021-06-23

Applicant: XILINX, INC.

Inventor： Ygal Arbel ,  Jonathan Jasper ,  Martin Newman

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673

Abstract: A memory controller includes transaction queue circuitry, a first skip event, a second skip event, a third skip event, and scheduler circuitry. The transaction queue circuitry is configured to store a first transaction, a second transaction, and a third transaction. The first transaction received is by the transaction queue circuitry before the second transaction and the third transaction. The second transaction is received by the transaction queue circuitry before the third transaction. The first skip event counter is associated with the first transaction. The second skip event counter is associated with the second transaction. The third skip event counter is associated with the third transaction. The scheduler circuitry is configured to select the third transaction before selecting the first transaction, increase a value of the first skip event counter based on selecting the third transaction before the first transaction, and communicate the third transaction to a memory device.

公开(公告)号：US11636061B2

公开(公告)日：2023-04-25

申请号：US17464642

申请日：2021-09-01

Applicant: XILINX, INC.

Inventor： Krishnan Srinivasan ,  Sagheer Ahmad ,  Ygal Arbel

IPC: G06F13/42 ,  G06F13/40

Abstract: Embodiments herein describe on-demand packetization where data that is too large to be converted directly into data words (DWs) for a chip-to-chip (C2C) interface are packetized instead. When identifying a protocol word that is larger than the DW of the C2C interface, a protocol layer can perform packetization where a plurality of protocol words are packetized and sent as a transfer. In one embodiment, the protocol layer removes some or all of the control data or signals in the protocol words so that the protocol words no longer exceed the size of the DW. These shortened protocol words can then be mapped to DWs and transmitted as separate packets on the C2C. The protocol layer can then collect the portion of the control data that was removed from the protocol words and transmit this data as a separate packet on the C2C interface.

公开(公告)号：US11327899B1

公开(公告)日：2022-05-10

申请号：US16933923

申请日：2020-07-20

Applicant: XILINX, INC.

Inventor： Ygal Arbel ,  Sagheer Ahmad ,  Gaurav Singh

IPC: G06F12/1027 ,  H03K19/1776

Abstract: An example programmable integrated circuit (IC) includes a processing system having a processor, a master circuit, and a system memory management unit (SMMU). The SMMU includes a first translation buffer unit (TBU) coupled to the master circuit, an address translation (AT) circuit, an AT interface coupled to the AT circuit, and a second TBU coupled to the AT circuit, and programmable logic coupled to the AT circuit in the SMMU through the AT interface.

公开(公告)号：US10713190B1

公开(公告)日：2020-07-14

申请号：US15729911

申请日：2017-10-11

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel

IPC: G06F12/0862 ,  G06F3/06 ,  G06F13/16

Abstract: Disclosed approaches for managing a translation look-aside buffer (TLB) have a bus master circuit that issues a read request that specifies a first virtual address of a first page. In response to a sequential access being identified and before data of the first page is returned, the bus master circuit issues a dummy read request that specifies a second virtual address of a second page. A TLB has mappings of virtual addresses to physical addresses, and a translation logic circuit translates virtual addresses to physical addresses. The translation logic circuit signals a miss in response to absence of a virtual address in the TLB. A control circuit in the MMU determines from a page table a mapping of a virtual address to a physical address in response to the signaled miss. The translation logic circuit updates the TLB circuit with the mapping.

公开(公告)号：US09990131B2

公开(公告)日：2018-06-05

申请号：US14493081

申请日：2014-09-22

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  Sagheer Ahmad ,  James J. Murray ,  Nishit Patel ,  Ahmad R. Ansari

IPC: G06F3/06 ,  G06F13/16 ,  G06F9/30

CPC classification number: G06F3/0604 ,  G06F3/0655 ,  G06F3/0683 ,  G06F9/3004 ,  G06F13/1657 ,  G06F2003/0697

Abstract: In an example, a circuit to manage memory between a first and second microprocessors each of which is coupled to a control circuit, includes: first and second memory circuits; and a switch circuit coupled to the first and second memory circuits, and memory interfaces of the first and second microprocessors, the switch circuit having a mode signal as input. The switch is configured to selectively operate in one of a first mode or a second mode based on the mode signal such that, in the first mode, the switch circuit couples the first memory circuit to the memory interface of the first microprocessor and the second memory circuit to the memory interface of the second microprocessor and, in the second mode, the switch circuit selectively couples the first or second memory circuits to the memory interface of either the first or second microprocessor.