公开(公告)号：US20060111802A1

公开(公告)日：2006-05-25

申请号：US11320610

申请日：2005-12-30

申请人： Natsuki Yokoyama ,  Yoshifumi Kawamoto ,  Eiichi Murakami ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Yoshio Kawamura

发明人： Natsuki Yokoyama ,  Yoshifumi Kawamoto ,  Eiichi Murakami ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Yoshio Kawamura

IPC分类号： G06F19/00

CPC分类号： C23C14/568 ,  C23C16/54 ,  G05B19/41865 ,  G05B2219/45031 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67173 ,  H01L21/67184 ,  H01L21/67276 ,  H01L21/67727 ,  H01L21/67745 ,  Y02P90/14 ,  Y02P90/20 ,  Y02P90/28 ,  Y10S414/135 ,  Y10S414/137 ,  Y10S438/908 ,  Y10T29/41

摘要： A fabricating method for a system including a plurality of processing apparatuses connected to each other by an inter-apparatus transporter. The semiconductor waters are processed in the processing apparatuses and are transported to specified processing apparatuses in different time interval that are set to N times a unit time interval. Since the fabricating system includes processing apparatuses and an inter-apparatus transporter that are periodically controlled at time intervals related to a unit time, intervals related to a unit time, the scheduling of a plurality of works can be made efficiently to enhance the level of optimization, thus improving the productivity.

公开(公告)号：US06897104B2

公开(公告)日：2005-05-24

申请号：US10452126

申请日：2003-06-03

申请人： Shimpei Tsujikawa ,  Toshiyuki Mine ,  Jiro Yugami ,  Natsuki Yokoyama ,  Tsuyoshi Yamauchi

发明人： Shimpei Tsujikawa ,  Toshiyuki Mine ,  Jiro Yugami ,  Natsuki Yokoyama ,  Tsuyoshi Yamauchi

IPC分类号： H01L21/316 ,  H01L21/318 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823462

摘要： A semiconductor device and a method for manufacturing the same of forming a silicon nitride film selectively without giving damages or contaminations to a surface of the silicon substrate thereby forming different types of gate dielectrics in one identical silicon substrate, are obtained by forming a silicon dioxide on the surface of a silicon substrate, then removing a portion thereof, forming a silicon nitride film to the surface of the substrate from which the silicon dioxide has been removed and, simultaneously, introducing nitrogen to the surface of the silicon dioxide which is left not being removed or, alternatively, depositing a silicon dioxide on the surface of the silicon substrate by chemical vapor deposition, then removing a portion thereof, forming a silicon nitride film on the surface of a substrate from which the silicon dioxide has been removed, and, simultaneously, introducing nitrogen to the surface of the silicon dioxide left not being removed, successively, dissolving and removing nitrogen-introduced silicon oxide film to expose the surface of the substrate and oxidizing the exposed surface of the silicon substrate and the silicon nitride film.

摘要翻译： 一种半导体器件及其制造方法，其选择性地形成氮化硅膜，而不会对硅衬底的表面造成损害或污染，从而在一个相同的硅衬底中形成不同类型的栅极电介质，通过在二氧化硅上形成二氧化硅 硅衬底的表面，然后去除其一部分，在已经除去二氧化硅的衬底的表面上形成氮化硅膜，同时将氮引入二氧化硅的不是 去除或者通过化学气相沉积在硅衬底的表面上沉积二氧化硅，然后去除其一部分，在去除二氧化硅的衬底的表面上形成氮化硅膜，同时 将氮气引入未被除去的二氧化硅的表面，依次溶解 并且移除氮导入的氧化硅膜以暴露衬底的表面并氧化硅衬底和氮化硅膜的暴露表面。

公开(公告)号：US20050029600A1

公开(公告)日：2005-02-10

申请号：US10942014

申请日：2004-09-16

申请人： Shimpei Tsujikawa ,  Toshiyuki Mine ,  Jiro Yugami ,  Natsuki Yokoyama ,  Tsuyoshi Yamauchi

发明人： Shimpei Tsujikawa ,  Toshiyuki Mine ,  Jiro Yugami ,  Natsuki Yokoyama ,  Tsuyoshi Yamauchi

IPC分类号： H01L21/316 ,  H01L21/318 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/44 ,  H01L21/8238 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L21/823857 ,  H01L21/823462

摘要： A semiconductor device and a method for manufacturing the same of forming a silicon nitride film selectively without giving damages or contaminations to a surface of the silicon substrate thereby forming different types of gate dielectrics in one identical silicon substrate, are obtained by forming a silicon dioxide on the surface of a silicon substrate, then removing a portion thereof, forming a silicon nitride film to the surface of the substrate from which the silicon dioxide has been removed and, simultaneously, introducing nitrogen to the surface of the silicon dioxide which is left not being removed or, alternatively, depositing a silicon dioxide on the surface of the silicon substrate by chemical vapor deposition, then removing a portion thereof, forming a silicon nitride film on the surface of a substrate from which the silicon dioxide has been removed, and, simultaneously, introducing nitrogen to the surface of the silicon dioxide left not being removed, successively, dissolving and removing nitrogen-introduced silicon oxide film to expose the surface of the substrate and oxidizing the exposed surface of the silicon substrate and the silicon nitride film

摘要翻译： 一种半导体器件及其制造方法，其选择性地形成氮化硅膜，而不会对硅衬底的表面造成损害或污染，从而在一个相同的硅衬底中形成不同类型的栅极电介质，通过在二氧化硅上形成二氧化硅 硅衬底的表面，然后去除其一部分，在已经除去二氧化硅的衬底的表面上形成氮化硅膜，同时将氮引入二氧化硅的不是 去除或者通过化学气相沉积在硅衬底的表面上沉积二氧化硅，然后去除其一部分，在去除二氧化硅的衬底的表面上形成氮化硅膜，同时 将氮气引入未被除去的二氧化硅的表面，依次溶解 并且去除引入氮的氧化硅膜以暴露衬底的表面并氧化硅衬底和氮化硅膜的暴露表面

公开(公告)号：US5820679A

公开(公告)日：1998-10-13

申请号：US713192

申请日：1996-09-12

申请人： Natsuki Yokoyama ,  Yoshifumi Kawamoto ,  Eiichi Murakami ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Yoshio Kawamura

发明人： Natsuki Yokoyama ,  Yoshifumi Kawamoto ,  Eiichi Murakami ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Yoshio Kawamura

IPC分类号： B65G49/07 ,  B23Q41/00 ,  B23Q41/02 ,  C23C14/56 ,  C23C16/54 ,  G05B19/418 ,  H01L21/00 ,  H01L21/02 ,  H01L21/027 ,  H01L21/205 ,  H01L21/285 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/677 ,  H01L21/68 ,  C23C16/00

CPC分类号： C23C14/568 ,  C23C16/54 ,  G05B19/41865 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67173 ,  H01L21/67184 ,  H01L21/67276 ,  H01L21/67727 ,  H01L21/67745 ,  G05B2219/45031 ,  Y02P90/14 ,  Y02P90/20 ,  Y02P90/28 ,  Y10S414/135 ,  Y10S414/137 ,  Y10S438/908 ,  Y10T29/41

摘要： Disclosed is a fabricating system including a plurality of processing apparatuses connected to each other by means of an inter-apparatus transporter, wherein one group of semiconductor wafers are processed in processing apparatuses and other group of wafers are transported to specified processing apparatuses for a time interval from (To+T) to a time To; and another group of wafers are processed and the remaining group of wafers are transported for a time interval from (To+T) to (To+2T). Since processing apparatuses can receive at least one of works from the inter-apparatus transporter for a time interval T min, the distribution of works from the transporter to processing apparatuses is completed for the time interval T min. The transporter is emptied for each time interval T min, and works are unloaded to the emptied transporter, which makes easy the scheduling, control and management of the transporting of a plurality of works in the fabricating system. Moreover, since the fabricating system including processing apparatuses is periodically controlled at a cycle time T min, the scheduling of a plurality of works can be made easy, to enhance the level of optimization, thus improving the productivity.

公开(公告)号：US08129802B2

公开(公告)日：2012-03-06

申请号：US12216359

申请日：2008-07-02

申请人： Hiroshi Fukuda ,  Tsukasa Fujimori ,  Natsuki Yokoyama ,  Yuko Hanaoka ,  Takafumi Matsumura

发明人： Hiroshi Fukuda ,  Tsukasa Fujimori ,  Natsuki Yokoyama ,  Yuko Hanaoka ,  Takafumi Matsumura

IPC分类号： H01L29/84

CPC分类号： B81C1/00246 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81C2203/0714 ,  B81C2203/0742

摘要： In the manufacturing technology of an integrated MEMS in which a semiconductor integrated circuit (CMOS or the like) and a micro machine are monolithically integrated on a semiconductor substrate, a technology capable of manufacturing the integrated MEMS without using a special process different from the normal manufacturing technology of a semiconductor integrated circuit is provided. A MEMS structure is formed together with an integrated circuit by using the CMOS integrated circuit process. For example, when forming an acceleration sensor, a structure composed of a movable mass, an elastic beam and a fixed beam is formed by using the CMOS interconnect technology. Thereafter, an interlayer dielectric and the like are etched by using the CMOS process to form a cavity. Then, fine holes used in the etching are sealed with a dielectric.

摘要翻译： 在半导体集成电路（CMOS等）和微机器单片集成在半导体基板上的集成MEMS的制造技术中，能够制造集成MEMS而不使用与正常制造不同的特殊工艺的技术 提供了半导体集成电路的技术。 通过使用CMOS集成电路工艺与集成电路一起形成MEMS结构。 例如，当形成加速度传感器时，通过使用CMOS互连技术形成由可移动质量块，弹性梁和固定梁构成的结构。 此后，通过使用CMOS工艺蚀刻层间电介质等以形成空腔。 然后，用电介质密封蚀刻中使用的细孔。

公开(公告)号：US07906796B2

公开(公告)日：2011-03-15

申请号：US12176635

申请日：2008-07-21

申请人： Kazuhiro Mochizuki ,  Hidekatsu Onose ,  Natsuki Yokoyama

发明人： Kazuhiro Mochizuki ,  Hidekatsu Onose ,  Natsuki Yokoyama

IPC分类号： H01L29/74

CPC分类号： H01L29/1608 ,  H01L29/0804 ,  H01L29/66068 ,  H01L29/7322

摘要： In a bipolar device, such as transistor or a thyristor, the emitter layer or the anode layer is formed of two high-doped and low-doped layers, a semiconductor region for suppressing recombination comprising an identical semiconductor having an impurity density identical with that of the low-doped layer is present being in contact with a base layer or a gate layer and a surface passivation layer, and the width of the semiconductor region for suppressing recombination is defined equal with or longer than the diffusion length of the carrier. This provides, among other things, an effect of attaining reduction in the size of the bipolar transistor or improvement of the switching frequency of the thyristor without deteriorating the performance.

摘要翻译： 在诸如晶体管或晶闸管的双极器件中，发射极层或阳极层由两个高掺杂和低掺杂层形成，用于抑制复合的半导体区域包括具有与 存在与基底层或栅极层和表面钝化层接触的低掺杂层，并且用于抑制复合的半导体区域的宽度被限定为等于或长于载体的扩散长度。 除此之外，这提供了在不降低性能的情况下实现双极晶体管的尺寸的减小或晶闸管的开关频率的提高的效果。

公开(公告)号：US07682990B2

公开(公告)日：2010-03-23

申请号：US11144593

申请日：2005-06-06

申请人： Hirotaka Hamamura ,  Toshiyuki Mine ,  Natsuki Yokoyama

发明人： Hirotaka Hamamura ,  Toshiyuki Mine ,  Natsuki Yokoyama

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28282 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/792

摘要： Conventionally, a MONOS type nonvolatile memory is fabricated by subjecting a silicon nitride film to ISSG oxidation to form a top silicon oxide film of ONO structure. If the ISSG oxidation conditions are severe, repeats of programming/erase operation cause increase of interface state density (Dit) and electron trap density. This does not provide a sufficient value of the on current, posing a problem in that the deterioration of charge trapping properties cannot be suppressed.For the solution to the problem, the silicon nitride film is oxidized by means of a high concentration ozone gas to form the top silicon oxide film.

摘要翻译： 通常，通过使氮化硅膜进行ISSG氧化来形成ONO结构的顶部氧化硅膜来制造MONOS型非易失性存储器。 如果ISSG氧化条件严重，编程/擦除操作的重复会导致界面态密度（Dit）和电子陷阱密度的增加。 这不能提供足够的导通电流值，这导致不能抑制电荷俘获特性的劣化的问题。 为了解决这个问题，氮化硅膜通过高浓度的臭氧气体被氧化，形成顶部氧化硅膜。

公开(公告)号：US20090064785A1

公开(公告)日：2009-03-12

申请号：US12216359

申请日：2008-07-02

申请人： Hiroshi Fukuda ,  Tsukasa Fujimori ,  Natsuki Yokoyama ,  Yuko Hanaoka ,  Takafumi Matsumura

发明人： Hiroshi Fukuda ,  Tsukasa Fujimori ,  Natsuki Yokoyama ,  Yuko Hanaoka ,  Takafumi Matsumura

IPC分类号： G01P15/125

CPC分类号： B81C1/00246 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81C2203/0714 ,  B81C2203/0742

摘要： In the manufacturing technology of an integrated MEMS in which a semiconductor integrated circuit (CMOS or the like) and a micro machine are monolithically integrated on a semiconductor substrate, a technology capable of manufacturing the integrated MEMS without using a special process different from the normal manufacturing technology of a semiconductor integrated circuit is provided. A MEMS structure is formed together with an integrated circuit by using the CMOS integrated circuit process. For example, when forming an acceleration sensor, a structure composed of a movable mass, an elastic beam and a fixed beam is formed by using the CMOS interconnect technology. Thereafter, an interlayer dielectric and the like are etched by using the CMOS process to form a cavity. Then, fine holes used in the etching are sealed with a dielectric.

摘要翻译： 在半导体集成电路（CMOS等）和微机器单片集成在半导体基板上的集成MEMS的制造技术中，能够制造集成MEMS而不使用与正常制造不同的特殊工艺的技术 提供了半导体集成电路的技术。 通过使用CMOS集成电路工艺与集成电路一起形成MEMS结构。 例如，当形成加速度传感器时，通过使用CMOS互连技术形成由可移动质量块，弹性梁和固定梁构成的结构。 此后，通过使用CMOS工艺蚀刻层间电介质等以形成空腔。 然后，用电介质密封蚀刻中使用的细孔。

公开(公告)号：US07325457B2

公开(公告)日：2008-02-05

申请号：US11492961

申请日：2006-07-26

申请人： Tsukasa Fujimori ,  Natsuki Yokoyama ,  Hiroshi Fukuda ,  Yuko Hanaoka ,  Takashi Azuma

发明人： Tsukasa Fujimori ,  Natsuki Yokoyama ,  Hiroshi Fukuda ,  Yuko Hanaoka ,  Takashi Azuma

IPC分类号： G01L9/12

CPC分类号： G01L9/0073 ,  B60C23/0408 ,  G01D5/2417 ,  G01L9/12 ,  G01L27/007

摘要： A sensor and sensor module with small power consumption and high reliability are disclosed. The sensor includes a capacitor having a capacitance varying with a physical quantity, a capacitance-voltage conversion circuit for converting the capacitance of the capacitor into a voltage, and a control signal generation circuit for generating a plurality of control signals. The capacitor has a frequency-capacitance characteristic with a resonant frequency. In a measurement of the physical quantity, the capacitance of the capacitor is measured with one of the control signals having a first frequency which is much higher or much lower than the resonant frequency. In a self-diagnosis of the sensor, the capacitance of the capacitor is measured with another one of the control signals having a second frequency which is equal or close to the resonant frequency.

摘要翻译： 公开了具有小功耗和高可靠性的传感器和传感器模块。 传感器包括具有物理量变化的电容的电容器，用于将电容器的电容转换为电压的电容 - 电压转换电路，以及用于产生多个控制信号的控制信号产生电路。 电容器具有谐振频率的频率 - 电容特性。 在物理量的测量中，电容器的电容被测量，其中一个控制信号具有比谐振频率高得多或低得多的第一频率。 在传感器的自诊断中，电容器的电容用另一个控制信号测量，其中第二频率等于或接近谐振频率。

公开(公告)号：US07306990B2

公开(公告)日：2007-12-11

申请号：US10535941

申请日：2003-11-28

申请人： Shinya Yamaguchi ,  Masahiko Ando ,  Toshikazu Shimada ,  Natsuki Yokoyama ,  Shunri Oda ,  Nobuyoshi Koshida

发明人： Shinya Yamaguchi ,  Masahiko Ando ,  Toshikazu Shimada ,  Natsuki Yokoyama ,  Shunri Oda ,  Nobuyoshi Koshida

IPC分类号： H01L21/336 ,  H01L21/00 ,  H01L29/788 ,  H01L21/3205 ,  H01L21/4763 ,  H01L29/76

CPC分类号： H01L29/7881 ,  G11C23/00

摘要： An information memory device capable of reading and writing of information by mechanical operation of a floating gate layer, in which a gate insulation film has a cavity (6), and a floating gate layer (5) having two stable deflection states in the cavity (6), the state stabilized by deflecting toward the channel side of transistor, and the state stabilized by deflecting toward the gate (7) side, writing and reading of information can be made by changing the stable deflection state of the floating gate layer (5) by Coulomb interactive force between the electrons (or positive holes 8) accumulated in the floating gate layer (5) and external electric field, and by reading the channel current change based on the state of the floating gate layer (5).

摘要翻译： 一种能够通过机械操作读取和写入信息的信息存储装置，其中栅极绝缘膜具有空腔（6）和在空腔中具有两个稳定偏转状态的浮动栅层（​​5） 6），通过偏转晶体管的沟道侧稳定状态，并且通过偏向栅极（7）而稳定的状态，可以通过改变浮动栅极层（5）的稳定偏转状态来进行信息的写入和读取 ）通过积存在浮动栅极层（5）中的电子（或正空穴8）与外部电场之间的库仑相互作用力，并且基于浮动栅极层（5）的状态读取沟道电流变化。