公开(公告)号：US06576928B2

公开(公告)日：2003-06-10

申请号：US09930144

申请日：2001-08-16

申请人： Masahiko Hiratani ,  Shinichiro Kimura ,  Tomoyuki Hamada

发明人： Masahiko Hiratani ,  Shinichiro Kimura ,  Tomoyuki Hamada

IPC分类号： H01L27108

CPC分类号： H01L21/02194 ,  H01L21/02183 ,  H01L21/02192 ,  H01L21/02271 ,  H01L21/31604 ,  H01L21/31691 ,  H01L27/10814 ,  H01L28/40

摘要： By using a solid solution of tantalum pentoxide and niobium pentoxide as a dielectric film installed between upper electrode and lower electrode in a capacitor which is used in a semiconductor device, the capacitor structure can be simplified to improve reliability of the semiconductor device while reducing the production cost thereof.

摘要翻译： 通过使用五氧化二钽和五氧化铌的固溶体作为安装在半导体器件中的电容器中的上电极和下电极之间的电介质膜，可以简化电容器结构以提高半导体器件的可靠性，同时减少生产 成本。

公开(公告)号：US06544834B1

公开(公告)日：2003-04-08

申请号：US09720002

申请日：2000-12-19

申请人： Yasuhiro Sugawara ,  Shinpei Iijima ,  Yuzuru Oji ,  Naruhiko Nakanishi ,  Misuzu Kanai ,  Masahiko Hiratani

发明人： Yasuhiro Sugawara ,  Shinpei Iijima ,  Yuzuru Oji ,  Naruhiko Nakanishi ,  Misuzu Kanai ,  Masahiko Hiratani

IPC分类号： H01L218242

CPC分类号： H01L27/1085 ,  H01L21/02183 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02337 ,  H01L21/02356 ,  H01L21/31604 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L28/40

摘要： An integrated semiconductor device has an improved reliability and is adapted to a higher degree of integration without reducing the accumulated electric charge of each information storage capacity element. The semiconductor device is provided with a DRAM having memory cells, each comprising an information storage capacity element C connected in series to a memory cell selection MISFET Qs formed on a main surface of a semiconductor substrate 1 and having a lower electrode 54, a capacity insulating film 58 and an upper electrode 59. The lower electrode 54 is made of ruthenium film oriented in a particular plane bearing, e.g., a (002) plane, and the capacity insulating film 58 is made of a polycrystalline tantalum film obtained by thermally treating an amorphous tantalum oxide film containing crystal of tantalum oxide in an as-deposited state for crystallization.

摘要翻译： 集成半导体器件具有改进的可靠性并且适于更高的集成度，而不减少每个信息存储电容元件的累积电荷。 半导体器件具有DRAM，其具有存储单元，每个DRAM包括与形成在半导体衬底1的主表面上的存储单元选择MISFET Qs串联连接的信息存储电容元件C，具有下电极54，电容绝缘 膜58和上电极59.下电极54由在特定平面轴承（例如（002））面取向的钌膜制成，并且电容绝缘膜58由通过热处理得到的多晶钽膜制成 含有沉淀状态的结晶用氧化钽晶体的无定形氧化钽膜。

公开(公告)号：US06521494B2

公开(公告)日：2003-02-18

申请号：US10211569

申请日：2002-08-05

申请人： Yuichi Matsui ,  Masahiko Hiratani ,  Yasuhiro Shimamoto ,  Yoshitaka Nakamura ,  Toshihide Nabatame

发明人： Yuichi Matsui ,  Masahiko Hiratani ,  Yasuhiro Shimamoto ,  Yoshitaka Nakamura ,  Toshihide Nabatame

IPC分类号： H01L218242

CPC分类号： H01L28/60 ,  H01L21/28562 ,  H01L27/10814

摘要： In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film. A dielectric film is formed on the lower electrodes and the deposition preventing film at a predetermined temperature. The material of the lower electrodes does not lose conduction even when exposed to the predetermined temperature employed for forming the dielectric film. Upper electrodes are further formed on the dielectric film. The upper and lower electrodes and an oxide dielectric film together constitute capacitors of the memory cells.

公开(公告)号：US06503791B2

公开(公告)日：2003-01-07

申请号：US09767706

申请日：2001-01-24

申请人： Yuichi Matsui ,  Masahiko Hiratani ,  Yasuhiro Shimamoto ,  Yoshitaka Nakamura ,  Toshihide Nabatame

发明人： Yuichi Matsui ,  Masahiko Hiratani ,  Yasuhiro Shimamoto ,  Yoshitaka Nakamura ,  Toshihide Nabatame

IPC分类号： H01L218242

CPC分类号： H01L28/60 ,  H01L21/28562 ,  H01L27/10814

摘要： In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film.

摘要翻译： 在包括多个存储单元的半导体器件中，在形成有多个孔的层间绝缘膜上形成防沉积膜，或者在层间绝缘膜和内表面上选择性地形成晶种膜， 孔的底面。 在发生底层依赖性的条件下，通过化学气相沉积在沉积防止膜上或通过利用种子膜在层间绝缘膜上沉积Ru，Ir或Pt的膜。 因此，根据防沉积膜或种子膜的图案形成下部电极。

公开(公告)号：US20090085086A1

公开(公告)日：2009-04-02

申请号：US12328046

申请日：2008-12-04

申请人： Yuichi Matsui ,  Masahiko Hiratani

发明人： Yuichi Matsui ,  Masahiko Hiratani

IPC分类号： H01L27/108

CPC分类号： H01L21/022 ,  C23C16/18 ,  C23C16/405 ,  C23C16/56 ,  H01L21/02175 ,  H01L21/02183 ,  H01L21/02194 ,  H01L21/02271 ,  H01L21/02356 ,  H01L21/31604 ,  H01L21/31637 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10882 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/56 ,  H01L28/75 ,  H01L28/90

摘要： The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600° C. or less, niobium pentoxide can suppress the oxidation of a bottom electrode and a barrier metal by heat treatment. However, according to heat treatment at low temperature, carbon incorporated from CVD sources into the film is not easily oxidized or removed. Therefore, a problem that leakage current increases arises. As an insulator film of a capacitor, a layered film composed of niobium pentoxide film and a tantalum pentoxide film, or a layered film composed of niobium pentoxide films is used. By the use of the niobium pentoxide film, the dielectric constant of the capacitor can be made high and the crystallization temperature can be made low. By multiple-stage formation of the dielectric film, leakage current can be decreased.

摘要翻译： 本发明涉及半导体电容器存储器件的电容器的结构，特别是五氧化二铌。 由于五氧化二铌具有600℃以下的低结晶温度，所以五氧化二铌可以通过热处理抑制底电极和阻挡金属的氧化。 然而，根据低温热处理，从CVD源引入到膜中的碳不易氧化或除去。 因此，出现漏电流增加的问题。 作为电容器的绝缘膜，使用由五氧化二铌膜和五氧化钽膜构成的层叠膜或由五氧化二铌膜构成的层叠膜。 通过使用五氧化二铌膜，可以使电容器的介电常数高，可以降低结晶温度。 通过电介质膜的多级形成，可以降低泄漏电流。

公开(公告)号：US07511327B2

公开(公告)日：2009-03-31

申请号：US11878475

申请日：2007-07-25

申请人： Yuichi Matsui ,  Masahiko Hiratani

发明人： Yuichi Matsui ,  Masahiko Hiratani

IPC分类号： H01L27/06

CPC分类号： H01L21/022 ,  C23C16/18 ,  C23C16/405 ,  C23C16/56 ,  H01L21/02175 ,  H01L21/02183 ,  H01L21/02194 ,  H01L21/02271 ,  H01L21/02356 ,  H01L21/31604 ,  H01L21/31637 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10882 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/56 ,  H01L28/75 ,  H01L28/90

摘要： The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600° C. or less, niobium pentoxide can suppress the oxidation of a bottom electrode and a barrier metal by heat treatment. However, according to heat treatment at low temperature, carbon incorporated from CVD sources into the film is not easily oxidized or removed. Therefore, a problem that leakage current increases arises. As an insulator film of a capacitor, a layered film composed of niobium pentoxide film and a tantalum pentoxide film, or a layered film composed of niobium pentoxide films is used. By the use of the niobium pentoxide film, the dielectric constant of the capacitor can be made high and the crystallization temperature can be made low. By multiple-stage formation of the dielectric film, leakage current can be decreased.

摘要翻译： 本发明涉及半导体电容器存储器件的电容器的结构，特别是五氧化二铌。 由于五氧化二铌具有600℃以下的低结晶温度，所以五氧化二铌可以通过热处理抑制底电极和阻挡金属的氧化。 然而，根据低温热处理，从CVD源引入到膜中的碳不易氧化或除去。 因此，出现漏电流增加的问题。 作为电容器的绝缘膜，使用由五氧化二铌膜和五氧化钽膜构成的层叠膜或由五氧化二铌膜构成的层叠膜。 通过使用五氧化二铌膜，可以使电容器的介电常数高，可以降低结晶温度。 通过电介质膜的多级形成，可以降低泄漏电流。

公开(公告)号：US20080265300A1

公开(公告)日：2008-10-30

申请号：US12213920

申请日：2008-06-26

申请人： Satoru Akiyama ,  Takao Watanabe ,  Yuichi Matsui ,  Masahiko Hiratani

发明人： Satoru Akiyama ,  Takao Watanabe ,  Yuichi Matsui ,  Masahiko Hiratani

IPC分类号： H01L27/108

CPC分类号： H01L27/10852 ,  H01L23/5223 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.

摘要翻译： DRAM的存储单元电容器（C 3）通过使用MIM电容器形成，该MIM电容器使用与逻辑电路（LOGIC）内的金属布线相同的层（M 3）的金属布线，从而使能 降低工艺成本。 通过使用高介电常数材料形成电容器并将其布置在其中形成位线（BL）的布线层上方，可以实现更高的积分。 此外，使用2T电池使得即使当它们以低电压工作时也可以提供足够的信号量。 通过对模拟（ANALOG）和存储器（MEM）中制造电容器的工艺进行通用化，可以以低成本在一个芯片上实现将逻辑，模拟和存储器安装在一起的半导体集成电路。

公开(公告)号：US07265407B2

公开(公告)日：2007-09-04

申请号：US11242911

申请日：2005-10-05

申请人： Yuichi Matsui ,  Masahiko Hiratani

发明人： Yuichi Matsui ,  Masahiko Hiratani

IPC分类号： H01L27/06

CPC分类号： H01L21/022 ,  C23C16/18 ,  C23C16/405 ,  C23C16/56 ,  H01L21/02175 ,  H01L21/02183 ,  H01L21/02194 ,  H01L21/02271 ,  H01L21/02356 ,  H01L21/31604 ,  H01L21/31637 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10882 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/56 ,  H01L28/75 ,  H01L28/90

摘要： The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600° C. or less, niobium pentoxide can suppress the oxidation of a bottom electrode and a barrier metal by heat treatment. However, according to heat treatment at low temperature, carbon incorporated from CVD sources into the film is not easily oxidized or removed. Therefore, a problem that leakage current increases arises. As an insulator film of a capacitor, a layered film composed of a niobium pentoxide film and a tantalum pentoxide film, or a layered film composed of niobium pentoxide films is used. By the use of the niobium pentoxide film, the dielectric constant of the capacitor can be made high and the crystallization temperature can be made low. By multiple-stage formation of the dielectric film, leakage current can be decreased.

摘要翻译： 本发明涉及半导体电容器存储器件的电容器的结构，特别是五氧化二铌。 由于五氧化二铌具有600℃以下的低结晶温度，所以五氧化二铌可以通过热处理抑制底电极和阻挡金属的氧化。 然而，根据低温热处理，从CVD源引入到膜中的碳不易氧化或除去。 因此，出现漏电流增加的问题。 作为电容器的绝缘膜，使用由五氧化二铌膜和五氧化二钽膜构成的层叠膜或由五氧化二铌膜构成的层叠膜。 通过使用五氧化二铌膜，可以使电容器的介电常数高，可以降低结晶温度。 通过电介质膜的多级形成，可以降低泄漏电流。

公开(公告)号：US07259058B2

公开(公告)日：2007-08-21

申请号：US10020314

申请日：2001-12-18

申请人： Yasuhiro Shimamoto ,  Masahiko Hiratani ,  Yuichi Matsui ,  Satoshi Yamamoto ,  Toshihide Nabatame ,  Toshio Ando ,  Hiroshi Sakuma ,  Shinpei Iijima

发明人： Yasuhiro Shimamoto ,  Masahiko Hiratani ,  Yuichi Matsui ,  Satoshi Yamamoto ,  Toshihide Nabatame ,  Toshio Ando ,  Hiroshi Sakuma ,  Shinpei Iijima

IPC分类号： H01L21/8242

CPC分类号： H01L28/60 ,  C23C16/18 ,  H01L21/28556 ,  H01L21/28568 ,  H01L28/55 ,  H01L28/91

摘要： A ruthenium electrode with a low amount of oxygen contamination and high thermal stability is formed by a chemical vapor deposition method. In the chemical vapor deposition method using an organoruthenium compound as a precursor, the introduction of an oxidation gas is limited to when the precursor is supplying, and the reaction is allowed to occur at a low oxygen partial pressure. Consequently, it is possible to form a ruthenium film with a low amount of oxygen contamination. Further, after formation of the ruthenium film, annealing at not less than the formation temperature is performed, thereby forming a ruthenium film with high thermal stability.

摘要翻译： 通过化学气相沉积法形成氧气污染少，热稳定性高的钌电极。 在使用有机钌化合物作为前体的化学气相沉积方法中，氧化气体的引入限于当前体供应时，并且允许反应在低氧分压下发生。 因此，可以形成氧含量低的钌膜。 此外，在形成钌膜之后，进行不低于形成温度的退火，由此形成热稳定性高的钌膜。

公开(公告)号：US07119407B2

公开(公告)日：2006-10-10

申请号：US10900430

申请日：2004-07-28

申请人： Yasuhiro Shimamoto ,  Katsunori Obata ,  Kazuyoshi Torii ,  Masahiko Hiratani

发明人： Yasuhiro Shimamoto ,  Katsunori Obata ,  Kazuyoshi Torii ,  Masahiko Hiratani

IPC分类号： H01L29/72

CPC分类号： H01L29/4983 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/02323 ,  H01L21/02329 ,  H01L21/02337 ,  H01L21/28061 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3141 ,  H01L21/3143 ,  H01L21/31612 ,  H01L21/3162 ,  H01L21/31641 ,  H01L21/31645 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545

摘要： In a method for manufacturing an FET having a gate insulation film with an SiO2 equivalent thickness of 2 nm or more and capable of suppressing the leak current to 1/100 or less compared with existent SiO2 films, an SiO2 film of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiO2 film is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.

摘要翻译： 在具有SiO 2等效厚度为2nm以上的栅极绝缘膜的FET的制造方法中，与现有的SiO 2相比，能够将漏电流抑制到1/100以下， 在Si衬底（多晶硅栅极）和高介电绝缘膜之间的边界处形成0.5nm或更大的SiO 2 SiO 2膜，并且形成 SiO 2膜比后续步骤中的源极 - 漏极活​​化热处理温度高。 因此，可以防止由静电电荷的产生产生的偏移阈值电压或由迁移率降低导致的漏极电流的降低，从而降低较小尺寸的场效应晶体管的电力消耗和增加电流。