公开(公告)号：US20100112765A1

公开(公告)日：2010-05-06

申请号：US12614632

申请日：2009-11-09

申请人： Hitoshi Yamaguchi ,  Takeshi Miyajima ,  Nozomu Akagi

发明人： Hitoshi Yamaguchi ,  Takeshi Miyajima ,  Nozomu Akagi

IPC分类号： H01L21/8238 ,  H01L21/8234

CPC分类号： H01L29/7813 ,  H01L21/823814 ,  H01L21/823885 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  Y10S438/977

摘要： A manufacturing method of a semiconductor device includes: forming multiple trenches on a semiconductor substrate; forming a second conductive type semiconductor film in each trench to provide a first column with the substrate between two trenches and a second column with the second conductive type semiconductor film in the trench, the first and second columns alternately repeated along with a predetermined direction; thinning a second side of the substrate; and increasing an impurity concentration in a thinned second side so that a first conductive type layer is provided. The impurity concentration of the first conductive type layer is higher than the first column. The first column provides a drift layer so that a vertical type first-conductive-type channel transistor is formed.

摘要翻译： 半导体器件的制造方法包括：在半导体衬底上形成多个沟槽; 在每个沟槽中形成第二导电类型的半导体膜，以提供具有在两个沟槽之间的衬底的第一柱和在沟槽中的第二导电型半导体膜的第二柱，第一和第二列与预定方向交替地重复; 减薄基板的第二面; 并增加稀薄第二侧的杂质浓度，从而提供第一导电类型层。 第一导电型层的杂质浓度比第一列高。 第一列提供漂移层，从而形成垂直型第一导电型沟道晶体管。

公开(公告)号：US20080173935A1

公开(公告)日：2008-07-24

申请号：US12003870

申请日：2008-01-03

申请人： Takeshi Miyajima

发明人： Takeshi Miyajima

IPC分类号： H01L29/06 ,  H01L21/329

CPC分类号： H01L29/7811 ,  H01L29/04 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/404 ,  H01L29/7808 ,  H01L29/7813 ,  H01L29/866 ,  Y10S438/931 ,  Y10S438/983

摘要： A semiconductor device includes a semiconductor substrate, a cell region, an outer peripheral region, a field plate, an outermost peripheral ring, outer peripheral region layer, an insulator film, and a Zener diode. The semiconductor substrate has a superjunction structure. The outer peripheral region is disposed at an outer periphery of the cell region. The Zener diode is disposed on the insulator film for electrically connecting the field plate with the outermost peripheral ring. The Zener diode has a first conductivity type region and a second conductivity type region that are alternately arranged in a direction from the cell region to the outer peripheral region.

摘要翻译： 半导体器件包括半导体衬底，单元区域，外周区域，场板，最外周环，外周区域层，绝缘膜和齐纳二极管。 半导体衬底具有超结构结构。 外围区域设置在电池区域的外周。 齐纳二极管设置在绝缘膜上，用于将场板与最外周环电连接。 齐纳二极管具有在从单元区域到外周区域的方向上交替布置的第一导电类型区域和第二导电类型区域。

公开(公告)号：US20070177444A1

公开(公告)日：2007-08-02

申请号：US11699579

申请日：2007-01-30

申请人： Takeshi Miyajima

发明人： Takeshi Miyajima

IPC分类号： G11C7/00

CPC分类号： H01L29/0684 ,  H01L21/02365 ,  H01L21/0262 ,  H01L21/02658 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7827

摘要： A semiconductor device having a super junction structure includes: multiple first columns extending in a current flowing direction; and multiple second columns extending in the current flowing direction. The first and second columns are alternately arranged in an alternating direction. Each first column provides a drift layer. The first and second columns have a boundary therebetween, from which a depletion layer expands in case of an off-state. At least one of the first columns and the second columns have an impurity dose, which is inhomogeneous by location with respect to the alternating direction.

摘要翻译： 具有超结结构的半导体器件包括：沿电流流动方向延伸的多个第一列; 以及沿电流流动方向延伸的多个第二列。 第一和第二列交替地沿交替的方向布置。 每个第一列提供漂移层。 第一和第二列之间具有边界，在断开状态的情况下，耗尽层从该边界扩展。 第一列和第二列中的至少一个具有杂质剂量，其相对于交替方向的位置不均匀。

公开(公告)号：US06548386B1

公开(公告)日：2003-04-15

申请号：US09570038

申请日：2000-05-12

申请人： Ichiharu Kondo ,  Yasuo Ishihara ,  Shuichi Nagahaka ,  Takeshi Miyajima

发明人： Ichiharu Kondo ,  Yasuo Ishihara ,  Shuichi Nagahaka ,  Takeshi Miyajima

IPC分类号： H01L2128

CPC分类号： H01L21/7685 ,  H01L21/76885 ,  H01L23/485 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2924/00014

摘要： Metallic films are formed on a silicon substrate on which an insulation film and a conductive portion are exposed. The metallic films include a first metallic film directly contacting the insulation film and the conductive portion and a second metallic film disposed on the first metallic film as a stress adjustment film to control a stress at an interface between the first metallic film and the underlying member. Accordingly, an adhesion between the first metallic film and the insulation film can be controlled to be smaller than that between the first metallic film and the conductive portion. Then, the metallic film is removed from the insulation film by an adhesive sheet selectively while remaining on the conductive portion. As a result, the metallic film can be patterned stably and readily at low cost.

摘要翻译： 金属膜形成在其上露出绝缘膜和导电部分的硅基板上。 金属膜包括直接接触绝缘膜和导电部分的第一金属膜和设置在第一金属膜上的第二金属膜作为应力调节膜，以控制第一金属膜和下层构件之间的界面处的应力。 因此，可以将第一金属膜和绝缘膜之间的粘合力控制为小于第一金属膜和导电部分之间的粘合力。 然后，通过粘合片选择性地将金属膜从绝缘膜上除去，同时保留在导电部分上。 结果，可以以低成本稳定且容易地构图金属膜。

公开(公告)号：US4785667A

公开(公告)日：1988-11-22

申请号：US10083

申请日：1987-02-11

申请人： Takeshi Miyajima ,  Takayuki Oshiro

发明人： Takeshi Miyajima ,  Takayuki Oshiro

IPC分类号： G01N29/11 ,  G01N29/265 ,  G01N29/44 ,  G01N29/04

CPC分类号： G01N29/4427 ,  G01N29/0645 ,  G01N29/11 ,  G01N29/265 ,  G01N2291/044 ,  G01N2291/2632

摘要： A method of measuring the inclining angle of a planar defect of a solid material with ultrasonic waves which includes the steps of irradiating ultrasonic waves incident to the planar defect of a solid material while longitudinally scanning a probe forwardly and backwardly. The inclining angle of the planar defect is determined based on the inclination of an echo envelope obtained from the relationship of the echo beam path distances of the ultrasonic waves versus the echo amplitudes or heights of the reflected waves reflected from the planar defect of the solid material. The inclining angle of the defect corresponds to a straight line portion of the echo envelope in a region where the echo height decreased gradually from a maximum height position as the echo beam path distance increases. Measurements can be made non-destructively with one probe and the inclining angle of the planar defect generated within an element or a member forming part of an electronic or mechanical apparatus can be determined accurately in an extremely efficient manner.

摘要翻译： PCT No.PCT / JP85 / 00225 Sec。 371日期1987年2月11日 102（e）日期1987年2月11日PCT提交1985年4月22日PCT公布。 出版物WO86 / 06486 日期：1986年11月6日。一种用超声波测量固体材料的平面缺陷的倾斜角的方法，包括以下步骤：在入射到固体材料的平面缺陷的同时照射超声波，同时向前和向后扫描探针 。 基于从超声波的回波光束路径距离与从固体材料的平面缺陷反射的反射波的回波幅度或高度获得的回波包络线的倾斜度来确定平面缺陷的倾斜角度 。 缺陷的倾斜角对应于回波高度随着回波光束路径距离的增加而从最大高度位置逐渐降低的区域中的回波包络线的直线部分。 可以用一个探针非破坏性地进行测量，并且可以以非常有效的方式精确地确定在元件内形成的平面缺陷的倾斜角或构成电子或机械装置的部件的部件。

公开(公告)号：US08008768B2

公开(公告)日：2011-08-30

申请号：US13024712

申请日：2011-02-10

申请人： Takeshi Miyajima

发明人： Takeshi Miyajima

IPC分类号： H01L23/34

CPC分类号： H01L24/94 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/367 ,  H01L23/4334 ,  H01L24/16 ,  H01L2221/68377 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/00

摘要： A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes: a casing, a board and a semiconductor chip. The chip includes: an element part; a heat sink bonded to the element part; an insulting layer located on the heat sink so that the heat sink is located between the element part and the insulating layer; and a side wall insulating layer covering all of end faces of the heat sink. The semiconductor chip is located between the casing and the board, so that the insulating layer is directed to the casing to enable heat radiation from the heat sink toward the casing via the insulating layer.

摘要翻译： 公开了一种半导体器件及其制造方法。 半导体器件包括：壳体，板和半导体芯片。 芯片包括：元件部分; 结合到元件部分的散热器; 位于所述散热器上的绝缘层，使得所述散热器位于所述元件部分和所述绝缘层之间; 以及覆盖散热器的所有端面的侧壁绝缘层。 半导体芯片位于壳体和板之间，使得绝缘层被引导到壳体以使得能够经由绝缘层从散热器向壳体的热辐射。

公开(公告)号：US07858475B2

公开(公告)日：2010-12-28

申请号：US12614632

申请日：2009-11-09

申请人： Hitoshi Yamaguchi ,  Takeshi Miyajima ,  Nozomu Akagi

发明人： Hitoshi Yamaguchi ,  Takeshi Miyajima ,  Nozomu Akagi

IPC分类号： H01L21/8234

CPC分类号： H01L29/7813 ,  H01L21/823814 ,  H01L21/823885 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  Y10S438/977

摘要： A manufacturing method of a semiconductor device includes: forming multiple trenches on a semiconductor substrate; forming a second conductive type semiconductor film in each trench to provide a first column with the substrate between two trenches and a second column with the second conductive type semiconductor film in the trench, the first and second columns alternately repeated along with a predetermined direction; thinning a second side of the substrate; and increasing an impurity concentration in a thinned second side so that a first conductive type layer is provided. The impurity concentration of the first conductive type layer is higher than the first column. The first column provides a drift layer so that a vertical type first-conductive-type channel transistor is formed.

摘要翻译： 半导体器件的制造方法包括：在半导体衬底上形成多个沟槽; 在每个沟槽中形成第二导电类型的半导体膜，以提供具有在两个沟槽之间的衬底的第一柱和在沟槽中的第二导电型半导体膜的第二柱，第一和第二列与预定方向交替地重复; 减薄基板的第二面; 并增加稀薄第二侧的杂质浓度，从而提供第一导电类型层。 第一导电型层的杂质浓度比第一列高。 第一列提供漂移层，从而形成垂直型第一导电型沟道晶体管。

公开(公告)号：US07635622B2

公开(公告)日：2009-12-22

申请号：US11889075

申请日：2007-08-09

申请人： Hitoshi Yamaguchi ,  Takeshi Miyajima

发明人： Hitoshi Yamaguchi ,  Takeshi Miyajima

IPC分类号： H01L21/8238

CPC分类号： H01L29/7813 ,  H01L21/823814 ,  H01L21/823885 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  Y10S438/977

摘要： A manufacturing method of a semiconductor device includes: forming multiple trenches on a semiconductor substrate; forming a second conductive type semiconductor film in each trench to provide a first column with the substrate between two trenches and a second column with the second conductive type semiconductor film in the trench, the first and second columns alternately repeated along with a predetermined direction; thinning a second side of the substrate; and increasing an impurity concentration in a thinned second side so that a first conductive type layer is provided. The impurity concentration of the first conductive type layer is higher than the first column. The first column provides a drift layer so that a vertical type first-conductive-type channel transistor is formed.

摘要翻译： 半导体器件的制造方法包括：在半导体衬底上形成多个沟槽; 在每个沟槽中形成第二导电类型的半导体膜，以提供具有在两个沟槽之间的衬底的第一柱和在沟槽中的第二导电型半导体膜的第二柱，第一和第二列与预定方向交替地重复; 减薄基板的第二面; 并增加稀薄第二侧的杂质浓度，从而提供第一导电类型层。 第一导电型层的杂质浓度比第一列高。 第一列提供漂移层，从而形成垂直型第一导电型沟道晶体管。

公开(公告)号：US20090227070A1

公开(公告)日：2009-09-10

申请号：US12379500

申请日：2009-02-24

申请人： Takeshi Miyajima

发明人： Takeshi Miyajima

IPC分类号： H01L21/50

CPC分类号： H01L24/94 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/367 ,  H01L23/4334 ,  H01L24/16 ,  H01L2221/68377 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/00

摘要： A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes: a casing, a board and a semiconductor chip. The chip includes: an element part; a heat sink bonded to the element part; an insulting layer located on the heat sink so that the heat sink is located between the element part and the insulating layer; and a side wall insulating layer covering all of end faces of the heat sink. The semiconductor chip is located between the casing and the board, so that the insulating layer is directed to the casing to enable heat radiation from the heat sink toward the casing via the insulating layer.

摘要翻译： 公开了一种半导体器件及其制造方法。 半导体器件包括：壳体，板和半导体芯片。 芯片包括：元件部分; 结合到元件部分的散热器; 位于所述散热器上的绝缘层，使得所述散热器位于所述元件部分和所述绝缘层之间; 以及覆盖散热器的所有端面的侧壁绝缘层。 半导体芯片位于壳体和板之间，使得绝缘层被引导到壳体以使得能够经由绝缘层从散热器向壳体的热辐射。

公开(公告)号：US5998268A

公开(公告)日：1999-12-07

申请号：US938472

申请日：1997-09-29

申请人： Yutaka Tomatsu ,  Takeshi Miyajima ,  Manabu Koike ,  Ryosuke Inoshita

发明人： Yutaka Tomatsu ,  Takeshi Miyajima ,  Manabu Koike ,  Ryosuke Inoshita

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/331 ,  H01L21/336 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/7397 ,  H01L29/66348 ,  H01L29/1095

摘要： On the surface of a semiconductor substrate there are formed a silicon oxide film, silicon nitride film and resist, whereby a groove is formed in the semiconductor substrate through an opening portion by chemical dry etching. An oxide film is formed on the inner surface of the groove by wet oxidation and, further, this oxide film is removed by wet etching, after which the surface of the semiconductor substrate located on the outer-peripheral side of the groove from an angular portion defined between a side surface of the groove and the surface of the semiconductor substrate is exposed. Then, the inner surface of the groove and the exposed surface of the semiconductor substrate are oxidized to thereby form a LOCOS oxide film, and thereafter this LOCOS oxide film is removed. As a result of this, the angular portion is made round, thereby enabling the avoidance of the concentration of an electric field on the angular portion of the groove.

摘要翻译： 在半导体衬底的表面上形成氧化硅膜，氮化硅膜和抗蚀剂，由此通过化学干蚀刻通过开口部分在半导体衬底中形成沟槽。 通过湿式氧化在沟槽的内表面上形成氧化膜，此外，通过湿蚀刻除去该氧化物膜，然后从位于槽的外周侧的半导体衬底的表面从角部 限定在凹槽的侧表面和半导体衬底的表面之间。 然后，将沟槽的内表面和半导体衬底的暴露表面氧化，从而形成LOCOS氧化物膜，然后除去该LOCOS氧化物膜。 其结果是，角部形成为圆形，从而能够避免沟槽的角部上的电场集中。