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    Memory and driving method of the same
    22.
    发明授权
    Memory and driving method of the same 有权
    内存和驱动方法相同

    公开(公告)号：US07352604B2

    公开(公告)日：2008-04-01

    申请号：US11607053

    申请日：2006-12-01

    申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

    发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

    IPC分类号： G11C17/00

    CPC分类号： G11C7/1096 ,  G11C7/1078 ,  G11C7/12 ,  G11C11/4094 ,  G11C17/12

    摘要： According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof are provided. The invention comprises a memory cell including a memory element in a region where a bit line and a word line cross with an insulator interposed between them, a column decoder, and a selector including a clocked inverter. An input node of the clocked inverter is connected to the bit line while an output node is connected to a data line. Among a plurality of transistors connected in series which form the clocked inverter, a gate of a P-type transistor of which source or drain is connected to a power source on the high potential side VDD and a gate of an N-type transistor of which source or drain is connected to a power source on the low potential side VSS are connected to the column decoder.

    摘要翻译： 根据本发明，通过减少元件的数量来减小安装面积并提高产量，并且提供了对外围电路的负担较小的存储器及其驱动方法。 本发明包括一个存储单元，其中存储单元包括位线和字线与插在它们之间的绝缘体交叉的区域中的存储元件，列解码器和包括时钟反相器的选择器。 时钟反相器的输入节点连接到位线，而输出节点连接到数据线。 在形成时钟反相器的串联连接的多个晶体管中，源极或漏极连接到高电位侧VDD上的电源的P型晶体管的栅极和N型晶体管的栅极 源极或漏极连接到低电位侧的电源VSS连接到列解码器。

    Circuit having source follower and semiconductor device having the circuit
    25.
    发明授权
    Circuit having source follower and semiconductor device having the circuit 失效

    公开(公告)号：US07081774B2

    公开(公告)日：2006-07-25

    申请号：US10893936

    申请日：2004-07-20

    申请人： Hiroyuki Miyake ,  Yutaka Shionoiri

    发明人： Hiroyuki Miyake ,  Yutaka Shionoiri

    IPC分类号： H03K19/0175 ,  H03K19/094 ,  H03K19/082 ,  G11C11/14 ,  G11C11/44

    CPC分类号： G09G3/20 ,  G09G2310/0275 ,  H03F1/301 ,  H03F3/505

    摘要： When a potential of a power supply line varies according to a flowing current, the gate-source voltage Vgs of a transistor also varies, leading to variations in the constant current between each source follower. In order to solve this problem, a potential Vb of the gate terminal of a transistor as a constant current source is changed in the same manner as a power supply line Vss which is connected to the source terminal of the transistor. Therefore, variations in the constant current are suppressed and variations in the output of the source followers are thus suppressed. In addition, by connecting the circuit having source followers to the output side of a signal line driver circuit, it can be prevented that luminance unevenness of a striped pattern is recognized in a display portion of a semiconductor device.

    Liquid crystal display device
    26.
    发明授权
    Liquid crystal display device 有权

    公开(公告)号：US07053969B2

    公开(公告)日：2006-05-30

    申请号：US10374999

    申请日：2003-02-28

    申请人： Shunpei Yamazaki ,  Shingo Eguchi ,  Yutaka Shionoiri ,  Etsuko Fujimoto

    发明人： Shunpei Yamazaki ,  Shingo Eguchi ,  Yutaka Shionoiri ,  Etsuko Fujimoto

    IPC分类号： G02F1/136

    CPC分类号： G02F1/133555 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2201/123 ,  H01L27/1255 ,  H01L29/42384

    摘要： It is an object to provide a display having high visibility and a transflective type liquid crystal display device having a reflection electrode having a concavo-convex structure formed without especially increasing the process. During manufacturing a transflective liquid crystal display device, a reflection electrode of a plurality of irregularly arranged island-like patterns and a transparent electrode of a transparent conductive film are layered in forming an electrode having transparent and reflection electrodes thereby having a concavo-convex form to enhance the scattering ability of light and hence the visibility of display. Furthermore, because the plurality of irregularly arranged island-like patterns can be formed simultaneous with an interconnection, a concavo-convex structure can be formed during the manufacturing process without especially increasing the patterning process only for forming a concavo-convex structure. It is accordingly possible to greatly reduce cost and improve productivity.

    Method for evaluating semiconductor device
    27.
    发明申请
    Method for evaluating semiconductor device 有权
    半导体器件评估方法

    公开(公告)号：US20050273290A1

    公开(公告)日：2005-12-08

    申请号：US11132434

    申请日：2005-05-19

    申请人： Etsuko Asano ,  Kiyoshi Kato ,  Yutaka Shionoiri ,  Masahiko Hayakawa

    发明人： Etsuko Asano ,  Kiyoshi Kato ,  Yutaka Shionoiri ,  Masahiko Hayakawa

    IPC分类号： G01R31/317 ,  G01R31/3187 ,  G06F19/00

    CPC分类号： G01R31/3187 ,  G01R31/31723 ,  G01R31/31725 ,  G01R31/31726

    摘要： The present invention provides a method for evaluating an intended element or a parameter. In addition, the invention provides an evaluation method for obtaining a more precise result rapidly. According to the invention, a plurality of evaluation circuits are formed over the same substrate, and while simultaneously operating the plurality of evaluation circuits, an output of one evaluation circuit selected by a selection circuit that is formed over the substrate is arbitrarily evaluated.

    摘要翻译： 本发明提供了一种用于评估预期元素或参数的方法。 此外，本发明提供了一种快速获得更精确结果的评估方法。 根据本发明，在相同的基板上形成多个评估电路，并且在同时操作多个评估电路的同时，任意地评估由形成在基板上的选择电路选择的一个评估电路的输出。

    Pulse output circuit, shift register and electronic equipment
    28.
    发明申请
    Pulse output circuit, shift register and electronic equipment 有权
    脉冲输出电路，移位寄存器和电子设备

    公开(公告)号：US20050062515A1

    公开(公告)日：2005-03-24

    申请号：US10958568

    申请日：2004-10-06

    申请人： Shou Nagao ,  Yoshifumi Tanada ,  Yutaka Shionoiri ,  Hiroyuki Miyake

    发明人： Shou Nagao ,  Yoshifumi Tanada ,  Yutaka Shionoiri ,  Hiroyuki Miyake

    IPC分类号： G02F1/1345 ,  G02F1/133 ,  G02F1/1368 ,  G06F1/04 ,  G09G3/20 ,  G09G3/36 ,  G11C19/00 ,  G11C19/28 ,  H01L51/50 ,  H03K3/013 ,  H03K3/353 ,  H03K17/00 ,  H03K17/693 ,  H03K19/0175 ,  H03L5/00 ,  H05B33/14

    CPC分类号： G11C19/28 ,  G09G3/3688 ,  G09G2310/0275 ,  G11C19/00

    摘要： A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTs 101 and 104 to turn ON the TFTs and a potential of a node α is raised. When the potential of the node α reaches (VDD−VthN), the node α becomes in a floating state. Accordingly, a TFT 105 is turned ON and a potential of an output node is raised as a clock signal becomes High level. On the other hand, a potential of a gate electrode of the TFT 105 is further raised due to an operation of a capacitance means 107 as the potential of the output node is raised, so that the potential of the gate electrode of the TFT 105 becomes higher than (VDD+VthN). Thus, the potential of the output node is raised to VDD without causing a voltage drop due to a threshold voltage of the TFT 105. An output at the subsequent stage is then inputted to a TFT 103 to turn the TFT 103 ON, while the potential of the node α of TFTs 102 and 106 is dropped to turn the TFT 105 OFF. As a result, the potential of the output node becomes Low level.

    摘要翻译： 一种显示装置的驱动电路，其包括单导电类型的TFT并输出具有正常振幅的输出信号。 一个脉冲被输入到TFT101和104，使TFT导通，并且提高节点α的电位。 当节点α的电位达到（VDD-VthN）时，节点α变为浮动状态。 因此，随着时钟信号变为高电平，TFT 105导通，输出节点的电位升高。 另一方面，随着输出节点的电位升高，由于电容装置107的操作，TFT 105的栅电极的电位进一步上升，使得TFT 105的栅电极的电位变为 高于（VDD + VthN）。 因此，输出节点的电位升高到VDD，而不会由于TFT 105的阈值电压引起电压降。然后，后级的输出被输入到TFT103，使TFT103导通，同时电位 的TFT102和106的节点α的下降以使TFT 105关闭。 结果，输出节点的电位变为低电平。