公开(公告)号：US07660143B2

公开(公告)日：2010-02-09

申请号：US12101266

申请日：2008-04-11

Applicant: Olivier Montfort ,  Sébastien Gaubert ,  Philippe Beliard

Inventor： Olivier Montfort ,  Sébastien Gaubert ,  Philippe Beliard

IPC: G11C17/12

CPC classification number: G11C11/5692 ,  G11C17/12 ,  G11C2211/5617

Abstract: The invention concerns a ROM comprising a set of memory points arranged in rows and columns, each memory point capable of storing two bits of data and comprising a single switch controllable to connect together first and second terminals of said switch, each of said first and second terminals being connected to one of first, second and third conductive lines, wherein said switch is connected via said first and second terminals between said first and second lines to encode a first data value, between said first and third lines to encode a second data value, between said second and third lines to encode a third data value, and both of said first and second terminals being connected to the same one of said first, second and third lines to encode a fourth data value.

Abstract translation: 本发明涉及一种ROM，其包括以行和列排列的一组存储器点，每个存储点能够存储两位数据，并且包括可控制以将所述开关的第一和第二端子连接在一起的单个开关，所述第一和第二 端子连接到第一，第二和第三导线之一，其中所述开关经由所述第一和第二端子在所述第一和第二线之间连接，以在所述第一和第三线之间编码第一数据值，以对第二数据值进行编码 ，在所述第二和第三行之间编码第三数据值，并且所述第一和第二终端都被连接到所述第一，第二和第三行中的相同的一个，以对第四数据值进行编码。

公开(公告)号：US5315149A

公开(公告)日：1994-05-24

申请号：US35765

申请日：1993-03-24

Applicant: Eric Compagne

Inventor： Eric Compagne

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H01L27/0251 ,  H01L27/0248

Abstract: A self-protected divider bridge in an integrated circuit comprising a P.sup.- substrate, a N.sup.- well, a P region forming a resistor, diffused in said well. A first and a second outmost contact and an intermediate contact are formed on the diffused region. A pad connected to the first contact receives an external voltage higher than the supply voltage of the integrated circuit. The reference potential of the integrated circuit is connected to the second contact and the substrate. A third contact formed on the well close to the first contact is connected to the first contact, and a fourth contact formed on the well close to the second contact is connected to the second contact.

Abstract translation: 集成电路中的自保护分压器桥，包括在所述阱中扩散的P-衬底，N阱，形成电阻器的P区。 在扩散区域上形成第一和第二最外面的触点和中间触点。 连接到第一触点的焊盘接收高于集成电路的电源电压的外部电压。 集成电路的参考电位连接到第二触点和基板。 在靠近第一触点的阱上形成的第三触点连接到第一触点，并且在靠近第二触点的阱上形成的第四触点连接到第二触点。

公开(公告)号：US10282214B2

公开(公告)日：2019-05-07

申请号：US15333704

申请日：2016-10-25

Applicant: DOLPHIN INTEGRATION

Inventor： Olivier Monfort ,  Lionel Jure ,  Gauthier Reveret ,  Sébastien Genevey

IPC: G06F1/08 ,  G06F1/10 ,  G06F1/32 ,  G06F9/445 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/3206

Abstract: The invention concerns a computing system comprising: a plurality of islands capable of operating in one of a plurality of operating modes, a first island being coupled to a first island control circuit and a second island being coupled to a second island control circuit; a first mediation circuit coupled to the first and second island control circuits and adapted: to receive a first request from the first island control circuit to change a current operating mode of the first island; to receive a second request from the second island control circuit to change a current operating mode of the second island; and to control a first voltage supply circuit and/or a first clock generator to change a voltage and/or clock signal supplied to the first and second islands based on the first and second requests.

公开(公告)号：US20180197585A1

公开(公告)日：2018-07-12

申请号：US15866156

申请日：2018-01-09

Applicant: Dolphin Integration

Inventor： Julien Louche ,  Olivier Mercier ,  Khaja Ahmad Shaik

IPC: G11C7/12 ,  G11C5/14 ,  G11C7/10

CPC classification number: G11C7/12 ,  G11C5/147 ,  G11C7/10 ,  G11C7/18 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/418 ,  G11C11/419

Abstract: A memory circuit having: a control circuit of a line of a memory array including: a first transistor coupled between first and second nodes and controlled by a line selection signal including a high level and a low level; a second transistor controlled by a first signal and coupled between the first node and a voltage supply rail of a first supply voltage, the first supply voltage being higher than the high level of the line selection signal, the first node being coupled to a line of memory array, the second node receiving a timing signal; and a line deactivation circuit adapted to generate the first signal and including a reference cell and a level shifter.

公开(公告)号：US09564208B2

公开(公告)日：2017-02-07

申请号：US14871508

申请日：2015-09-30

Applicant: Dolphin Integration

Inventor： Oron Chertkow ,  Ariel Pescovsky

IPC: G11C14/00 ,  G11C11/412 ,  G11C16/04 ,  G11C16/10 ,  G11C5/00 ,  G11C29/00

CPC classification number: G11C11/4125 ,  G11C5/005 ,  G11C14/00 ,  G11C16/0441 ,  G11C16/10 ,  G11C29/789

Abstract: The invention concerns a memory cell having: first and second cross-coupled gated inverters (102, 104), each including first and second inputs (IN1, IN2) and an output (OUT) and being adapted to couple its output to a first logic level only when the first and second inputs both receive the inverse of the first logic level; a first cut-off circuit (106) coupling the second input (IN2) of the first gated inverter (102) to the first input (IN1) of the first gated inverter (102); and a second cut-off circuit (108) coupling the second input (IN2) of the second gated inverter (104) to the first input (IN1) of the second gated inverter (104).

Abstract translation: 本发明涉及一种存储器单元，其具有：第一和第二交叉耦合门控反相器（102,104），每个反相器包括第一和第二输入（IN1，IN2）和输出（OUT），并且适于将其输出耦合到第一逻辑 只有当第一和第二输入都接收到第一逻辑电平的反相时; 将第一选通逆变器（102）的第二输入（IN2）与第一选通逆变器（102）的第一输入（IN1）耦合的第一截止电路（106）; 以及将第二选通逆变器（104）的第二输入（IN2）与第二门控逆变器（104）的第一输入（IN1）耦合的第二截止电路（108）。

公开(公告)号：US09269423B2

公开(公告)日：2016-02-23

申请号：US14051357

申请日：2013-10-10

Applicant: DOLPHIN INTEGRATION

Inventor： Ilan Sever

IPC: G11C7/10 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  G11C29/08 ,  G11C7/22

CPC classification number: G11C11/412 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/418 ,  G11C11/419 ,  G11C29/08

Abstract: The invention concerns a memory array having memory cells arranged in columns and rows, the memory cells of each column being coupled to at least one common write line of their column, the memory cells of each row being coupled to a common selection line of their row, wherein each of the memory cells includes a latch formed of a pair of inverters cross-coupled between first and second storage nodes; a first transistor coupled between the first storage node and a first test data input; and a second transistor coupled between the second storage node and a second test data input.

Abstract translation: 本发明涉及具有以列和行排列的存储单元的存储器阵列，每列的存储单元耦合到其列的至少一个公共写入线，每行的存储单元耦合到其行的公共选择行 其中每个存储单元包括由在第一和第二存储节点之间交叉耦合的一对反相器形成的锁存器; 耦合在第一存储节点和第一测试数据输入之间的第一晶体管; 以及耦合在所述第二存储节点和第二测试数据输入之间的第二晶体管。

公开(公告)号：US08446155B2

公开(公告)日：2013-05-21

申请号：US12672612

申请日：2008-08-05

Applicant: Florian Espalieu ,  Paul Giletti ,  Frédéric Poullet

Inventor： Florian Espalieu ,  Paul Giletti ,  Frédéric Poullet

IPC: G01R29/26

CPC classification number: G01R31/3167 ,  G01R31/2841 ,  G01R31/3004 ,  H03K3/84

Abstract: The invention relates to a test device for an analog circuit to be mounted on a mixed circuit including said analog circuit and a synchronous digital circuit. The test device includes a disturbance emulator connected to a first supply source (UrefD) capable of disturbing a second supply source (UrefA) of the analog circuit, the first and second supply sources being optionally merged, the emulator being adapted for receiving data representative of the evolution, during a given duration, of the average (μI) and the typical deviation (σI) of a first inrush current (I) that would be applied to the first supply source by the digital circuit, and being adapted for applying to the first supply source during successive intervals, each successive interval having said duration, a second inrush current (Irep) equal to the sum of the average and of the product of the typical deviation and of a pseudo-random signal varying according to a Gaussian law.

Abstract translation: 本发明涉及一种用于将模拟电路安装在包括所述模拟电路和同步数字电路的混合电路上的测试装置。 测试装置包括连接到能够干扰模拟电路的第二电源（UrefA）的第一电源（UrefD）的干扰仿真器，所述第一和第二电源可选地被合并，所述仿真器适于接收代表 在给定持续时间内，由数字电路施加到第一电源的第一浪涌电流（I）的平均值（μI）和典型偏差（sigma）的演化，并适用于 在连续间隔期间的第一供电源，每个连续间隔具有所述持续时间，第二涌入电流（Irep）等于典型偏差的平均值乘积和根据高斯定律变化的伪随机信号的乘积之和。

公开(公告)号：US07443322B2

公开(公告)日：2008-10-28

申请号：US11588857

申请日：2006-10-27

Applicant: Eric Compagne

Inventor： Eric Compagne

IPC: H03M1/10

CPC classification number: H03M3/378 ,  H03M3/458

Abstract: A device for testing an analog-to-digital converter providing a digital signal at a given sampling frequency, comprising a unit for providing a test signal to the converter, the test signal being a periodic signal comprising frequency components only at a fundamental frequency and at harmonics of the fundamental frequency, the fundamental frequency being a multiple of one quarter of the sampling frequency; a filter capable of receiving the digital signal and of rejecting the fundamental frequency to provide a filtered digital signal; and a unit capable of receiving the digital signal and the filtered digital signal and of providing a signal representative of the ratio between the effective powers of the digital signal and of the filtered digital signal.

Abstract translation: 一种用于测试以给定采样频率提供数字信号的模数转换器的装置，包括用于向转换器提供测试信号的单元，测试信号是包括仅在基频和 基频的谐波，基频是采样频率四分之一的倍数; 滤波器，其能够接收所述数字信号并拒绝所述基频以提供经滤波的数字信号; 以及能够接收数字信号和经滤波的数字信号并且提供表示数字信号的有效功率与滤波数字信号之间的比率的信号的单元。

公开(公告)号：US5982234A

公开(公告)日：1999-11-09

申请号：US944454

申请日：1997-10-06

Applicant: Eric Compagne

Inventor： Eric Compagne

IPC: H03F1/26 ,  H03F1/34 ,  H03F3/45

CPC classification number: H03F1/26 ,  H03F3/45475 ,  H03F3/45977 ,  H03F2200/186 ,  H03F2200/372 ,  H03F2203/45526

Abstract: The invention relates to an arrangement comprising a main amplifier (1, 10) and means (5) for creating, at least during predetermined periods, a floating references voltage (V.sub.G) for applying at least one input signal (V') on at least one first input terminal (E-, E) of the main amplifier, said reference voltage (V.sub.G) being servo-controlled to the equivalent input noise (Vn) of the main amplifier.

Abstract translation: 本发明涉及一种包括主放大器（1,10）和装置（5）的装置，用于至少在预定时段期间至少在至少在预定时段内产生用于至少施加至少一个输入信号（V'）的浮动参考电压（VG） 主放大器的一个第一输入端（E，E），所述参考电压（VG）被伺服控制到主放大器的等效输入噪声（Vn）。

公开(公告)号：US5119418A

公开(公告)日：1992-06-02

申请号：US703657

申请日：1991-05-21

Applicant: Christian Dupillier

Inventor： Christian Dupillier

IPC: H04Q5/00 ,  H04M1/723 ,  H04M3/527 ,  H04M9/02 ,  H04Q1/442

CPC classification number: H04M3/527 ,  H04M1/723 ,  H04M9/02 ,  H04Q1/4423

Abstract: In a telephone system, several telephone terminals are connected to a single telephone line including several telephone interface circuits (6, 7, 8), each interface circuit being energized by ringing signals appearing on the line and being arranged between the telephone line (3) and one of the telephone terminals (13, 14, 15, 16), the ring of which is disconnected from the line. Each interface circuit comprises a circuit (26) for counting ringing signals and picking up the line, this first circuit receiving at the input the ringing signals appearing on the line (L1-L2) during a telephone call, and counting a predetermined number of these ringing signals, then picking up the line by a relay (27) at the moment the last ringing signal counted stops. The system is powered only by the signals on the telephone line.

Abstract translation: 在电话系统中，若干电话终端连接到包括几个电话接口电路（6,7,8）的单个电话线，每个接口电路通过振铃出现在线路上的信号而被激励，并且被布置在电话线路（3） 和电话终端（13,14,15,16）中的一个，其环与线路断开。 每个接口电路包括用于对振铃信号进行计数并拾取线路的电路（26），该第一电路在电话接收期间在输入端接收出现在线路（L1-L2）上的振铃信号，并且对这些信号进行计数 振铃信号，然后在最后一个振铃信号计数停止时由继电器（27）拾起线路。 系统仅由电话线上的信号供电。