公开(公告)号：US08963430B2

公开(公告)日：2015-02-24

申请号：US13451457

申请日：2012-04-19

Applicant: James T Walker

Inventor： James T Walker

IPC: H05B37/02 ,  H05B33/08

CPC classification number: H05B33/0893

Abstract: A circuit is disclosed for determining which of a multiplicity of LED strings in an illumination system has a fault. A group of circuits determines the maximum, minimum, midpoint between maximum and minimum, and average voltage of the group of LED string voltages in use, and examines the statistical properties of the LED string voltages. Comparators are used to find the strings which have the highest and lowest operating voltages, and to compare the midpoint and average voltages to determine whether the highest or lowest voltage string is responsible for causing a fault in the illumination system operation. Memory means are used to keep the said determined string turned off to prevent faulty operation.

Abstract translation: 公开了一种用于确定照明系统中多个LED串中的哪一个具有故障的电路。 一组电路确定最大值和最小值之间的最大值，最小值，最小值以及所使用的LED串电压组的平均电压，并检查LED串电压的统计特性。 比较器用于找到具有最高和最低工作电压的串，并且比较中点和平均电压以确定最高或最低电压串是否导致照明系统操作中的故障。 存储装置用于保持所述确定的字符串被关闭以防止错误的操作。

公开(公告)号：US07186594B2

公开(公告)日：2007-03-06

申请号：US11183640

申请日：2005-07-18

Applicant: Randy L. Yach ,  Gregg Dix

Inventor： Randy L. Yach ,  Gregg Dix

IPC: H01L21/332

CPC classification number: H01L27/0259

Abstract: A high voltage ESD-protection structure is used to protect delicate transistor circuits connected to an input or output of an integrated circuit bond pad from destructive high voltage ESD events by conducting at a controlled breakdown voltage that is less than a voltage that may cause destructive breakdown of the input and/or output circuits. The ESD-protection structure is able to absorb high current from these ESD events without snapback that would compromise operation of the higher voltage inputs and/or outputs of the integrated circuit. The ESD-protection structure will conduct when an ESD event occurs at a voltage above a controlled breakdown voltage of an electronic device, e.g., diode, in the ESD protection structure. Conduction of current from an ESD event having a voltage above the electronic device controlled breakdown voltage may be through another electronic device, e.g., transistor, having high current conduction capabilities, in the ESD-protection structure that may be controlled (triggered) by the device (e.g., diode) determining the controlled breakdown voltage (at which the ESD voltage is clamped to a desired value). The high voltage ESD-protection structure may be located substantially under the bond pad and may also include a low capacitance forward diode structure between the bond pad and the ESD clamp circuit.

Abstract translation: 高压ESD保护结构用于通过在可能导致破坏性击穿的电压下进行受控击穿电压来保护连接到集成电路接合焊盘的输入或输出的精细晶体管电路免受破坏性高电压ESD事件的影响 的输入和/或输出电路。 ESD保护结构能够吸收来自这些ESD事件的高电流，而不会产生危及集成电路的较高电压输入和/或输出的操作的快速恢复。 当ESD事件发生在高于ESD保护结构中电子器件（例如二极管）的受控击穿电压的电压时，ESD保护结构将导通。 来自具有高于电子器件受控击穿电压的电压的ESD事件的电流的导通可以通过可由该器件控制（触发）的ESD保护结构中的另一电子器件，例如具有高电流传导能力的晶体管 （例如，二极管）确定受控击穿电压（ESD电压被钳位到期望值）。 高压ESD保护结构可以基本上位于接合焊盘下方，并且还可以包括在接合焊盘和ESD钳位电路之间的低电容正向二极管结构。

公开(公告)号：US07157890B1

公开(公告)日：2007-01-02

申请号：US11385374

申请日：2006-03-21

Applicant: Bryan Kris

Inventor： Bryan Kris

IPC: G05F1/595

CPC classification number: H02J1/102

Abstract: A plurality of power supply modules having their outputs coupled in parallel are controlled for load balancing purposes through a direct current bus having filtered pulse width modulation (PWM) signals representative of the power outputs of each of the plurality of power supply modules. A local PWM signal for each of the plurality of power supply modules is filtered to a DC voltage and used to compare with an average power required from each of the plurality of power supply modules.

Abstract translation: 通过具有代表多个电源模块中每个电源模块的功率输出的已滤波的脉冲宽度调制（PWM）信号的直流总线，控制具有并联耦合的多个电源模块用于负载平衡目的。 用于多个电源模块中的每一个的本地PWM信号被滤波成DC电压并用于与多个电源模块中的每一个所需的平均功率进行比较。

公开(公告)号：US07157790B2

公开(公告)日：2007-01-02

申请号：US10209502

申请日：2002-07-31

Applicant: Bruce Beauchamp ,  Andrew Tuthill ,  Joseph D. Fernandez ,  Anucha Phongsantichai

Inventor： Bruce Beauchamp ,  Andrew Tuthill ,  Joseph D. Fernandez ,  Anucha Phongsantichai

IPC: H01L31/00

CPC classification number: H01L24/49 ,  H01L23/4952 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2224/48755 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/4911 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/85201 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An integrated circuit device comprising an integrated circuit die mounted on a leadframe having a plurality of inner leads. The integrated circuit die has a plurality of bond pads that are electrically connected to the inner leads of the leadframe, wherein at least two bond pads are connected to a one of the plurality of inner leads and/or at least two inner leads are connected to one or more bond pads with a single bond wire. A single bond wire is connected to a first bond pad or inner lead and subsequently wedge or stitch bonded to a second bond pad or inner lead, then it is connected to a third bond pad or inner lead. The single bond wire requires only one connection area at each of the bond pad(s) and inner lead(s). The bond pad(s) of the die and inner lead(s) of the leadframe are thereby electrically connected together by the single bond wire.

Abstract translation: 一种集成电路装置，包括安装在具有多个内引线的引线框上的集成电路管芯。 集成电路管芯具有电连接到引线框架的内部引线的多个接合焊盘，其中至少两个接合焊盘连接到多个内部引线中的一个和/或至少两个内部引线连接到 一个或多个具有单键线的接合焊盘。 单键线连接到第一接合焊盘或内引线，随后楔形或缝合接合到第二接合焊盘或内引线，然后连接到第三接合焊盘或内引线。 单键线在每个接合焊盘和内引线上仅需要一个连接区域。 因此，引线框架的管芯和内引线的接合焊盘由单键焊丝电连接在一起。

公开(公告)号：US20030179820A1

公开(公告)日：2003-09-25

申请号：US09972558

申请日：2001-10-08

Applicant: Microchip Technology Inc.

Inventor： Thomas J. Bombard

IPC: H04Q001/20 ,  H04B003/46

CPC classification number: G01R23/16

Abstract: A spectrum analyzer that may be implemented by a simple microcontroller that does not have a hardware multiply function is disclosed. The spectrum analyzer of the present invention utilizes at least five frequency bins. The input signal is sampled at four times the bin frequency. The input signal is sampled at twice the Nyquist rate, which results in symmetries in the sin(wn) and cos(wn) functions. These symmetries allow the in-phase and quadrature components of the input signal to be calculated by add, ignore or subtract operations instead of the more complex multiplication and integration operations. Accordingly, the energy for each bin may be calculated with a minimum number of multiply operations. Because the number of multiply operations have been significantly reduced, these multiply operations may be performed by software instead of hardware. As a result, the spectrum analyzer may be implemented with a simple processor that does not have a hardware multiply. Another frequency bin is added by oversampling the highest frequency. A low pass filter is used to eliminate the effect of aliasing on the other frequency bins. A simple processor can still handle a bin that has been processed in this manner. As a result, at least five frequency bins may be processed by a spectrum analyzer implemented on a simple processor.

Abstract translation: 公开了可以由不具有硬件乘法功能的简单微控制器实现的频谱分析仪。 本发明的频谱分析仪使用至少五个频率分
组。 输入信号以四倍的频率采样。 输入信号以奈奎斯特速率的两倍采样，这导致sin（wn）和cos（wn）函数中的对称性。 这些对称性允许输入信号的同相和正交分量通过加法，忽略或减法运算而不是更复杂的乘法和积分运算来计算。 因此，可以用最小的乘法运算来计算每个仓的能量。 由于乘法运算的数量已经大大减少，所以这些乘法运算可以由软件代替硬件执行。 结果，频谱分析仪可以用不具有硬件乘法的简单处理器来实现。 通过过采样最高频率来添加另一个频率仓。 低通滤波器用于消除混叠对其他频率仓的影响。 一个简单的处理器仍然可以处理已经以这种方式处理的bin。 结果，至少五个频率仓可以由在简单处理器上实现的频谱分析仪处理。

公开(公告)号：US6151238A

公开(公告)日：2000-11-21

申请号：US256598

申请日：1999-02-23

Applicant: Willem Smit ,  Paul Hofhine ,  Clark Rogers

Inventor： Willem Smit ,  Paul Hofhine ,  Clark Rogers

IPC: H01L23/544 ,  G11C17/00

CPC classification number: H01L23/544 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2924/0002

Abstract: An integrated circuit having a microcontroller, mask programmed read only memory, functions such as clock oscillator, analog-to-digital converter, timers, etc., where each may be adjusted with a digital input to a desired calibration value. The digital input resulting in the desired calibration value being stored in a programmable fuse array.

Abstract translation: 具有微控制器，掩模编程的只读存储器，诸如时钟振荡器，模数转换器，定时器等功能的集成电路，其中每个可以用数字输入调整到期望的校准值。 导致所需校准值的数字输入被存储在可编程熔丝阵列中。

公开(公告)号：US5446864A

公开(公告)日：1995-08-29

申请号：US207886

申请日：1994-03-07

Applicant: Martin Burghardt ,  Eric Berman ,  Ajay Padgaonkar ,  Ray Allen

Inventor： Martin Burghardt ,  Eric Berman ,  Ajay Padgaonkar ,  Ray Allen

IPC: G06F12/14

CPC classification number: G06F12/1433

Abstract: A microcontroller fabricated on a semiconductor chip has an on-chip EPROM program memory. The microcontroller is selectively configurable to operate in any one of a plurality of predetermined operating modes, including at least one secure microcontroller mode. A plurality of EPROM configuration fuses used for configuring the microcontroller and protecting its program memory from read, verify or write through any instruction initiated from other than a predetermined secure area of the chip, are mapped into the on-chip EPROM program memory as bits in respective address locations thereof. The value of a bit representing any one of said fuses is effective to determine the condition of the respective fuse. That condition is observed by reading the value of the respective bit for that fuse stored in the EPROM program memory. The chip security is enabled by configuring the microcontroller in a code protected mode by programming the bits representing the desired fuses in the EPROM program memory to effectively blow or erase each fuse according to the desired configuration.

Abstract translation: 在半导体芯片上制造的微控制器具有片上EPROM程序存储器。 微控制器被选择性地配置为以多个预定操作模式中的任一种操作，包括至少一个安全微控制器模式。 用于配置微控制器并保护其程序存储器的多个EPROM配置保险丝不被从芯片的预定安全区域以外发起的任何指令的读取，验证或写入，被映射到片上EPROM程序存储器中，作为 各自的地址位置。 表示任何一个所述保险丝的位的值对于确定相应保险丝的状态是有效的。 通过读取存储在EPROM程序存储器中的该熔丝的相应位的值来观察该条件。 通过将代表EPROM程序存储器中所需保险丝的位编程为根据所需配置有效地吹扫或擦除每个保险丝，可以通过将代码保护模式中的微控制器配置为芯片安全性。

公开(公告)号：US5033025A

公开(公告)日：1991-07-16

申请号：US454137

申请日：1989-12-21

Applicant: Ajay J. Padgaonkar

Inventor： Ajay J. Padgaonkar

IPC: G11C7/10 ,  G11C7/20

CPC classification number: G11C7/1084 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/20

Abstract: A semiconductor integrated circuit device has an on-chip processor and at least one on-chip digital register for storing plural bits therein. The bit contents of the register are written, selectively transformed, and read out of the register during processing of data by the processor and related circuitry. Peripheral instructions such as those from an interrupt source may contend with instructions from the processor for setting and clearing one or more bits in the register. To permit setting and clearing a unique bit in the register without affecting other bits in the register or the capability of the contending source to perform its instructions on one or more of these other bits, three separate addresses are provided for bit set, bit clear, and direct write of the register.

Abstract translation: 半导体集成电路器件具有片上处理器和用于在其中存储多个位的至少一个片上数字寄存器。 在由处理器和相关电路处理数据期间，寄存器的位内容被写入，选择性地变换和从寄存器中读出。 来自中断源的外设指令可以与来自处理器的指令相抵触，用于设置和清除寄存器中的一个或多个位。 为了允许设置和清除寄存器中的唯一位，而不影响寄存器中的其他位或竞争源在其中一个或多个位上执行其指令的能力，为位置1，位清零提供三个单独的地址， 并直接写入寄存器。

公开(公告)号：US12192079B2

公开(公告)日：2025-01-07

申请号：US18202899

申请日：2023-05-27

Applicant: Microchip Technology Inc.

Inventor： Scott Muma ,  Winston Mok ,  Steven Scott Gorshe

IPC: H04L43/062 ,  H04L43/0894 ,  H04L7/04 ,  H04L12/70

Abstract: A method and apparatus in which a data stream is received that includes constant bit rate (CBR) carrier streams, at least one of which comprises frames, a cumulative phase offset report (CPOR) and a client rate report (CRR). A counter accumulating a PHY-scaled stream clock (IPSCk) is sampled at a nominal sampling period (Tps) to obtain a cumulative PHY-scaled count (CPSC). A PHY-scaled stream phase offset (PSPO) is calculated that indicates phase difference between PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD). The data stream is demultiplexed to obtain CBR carrier streams. Respective CBR carrier streams include a previous network node CPOR (CPOR-P) and a previous network node CPO (CPO-P). A CPO is calculated that is a function of CPO-P and PSPO. CPO-P is replaced with the calculated CPO. The CBR carrier streams are multiplexed into intermediate-network-node data streams that are transmitted from the intermediate-network-node.

公开(公告)号：US12154622B2

公开(公告)日：2024-11-26

申请号：US17736563

申请日：2022-05-04

Applicant: Microchip Technology Inc.

Inventor： Victor Nguyen ,  Fethi Dhaoui ,  John L McCollum ,  Fengliang Xue

IPC: G11C13/00 ,  H10N70/00 ,  H10N70/20

Abstract: A ReRAM memory array includes ReRAM memory cells having two series-connected select transistors connected in series with a ReRAM device. When ReRAM memory cell(s) are selected for erasing, the bit line coupled to the ReRAM memory cell(s) to be erased is biased at a first voltage potential. The source line coupled to the ReRAM memory cell(s) to be erased is biased at a second voltage potential greater than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to erase the ReRAM device. The gates of the series-connected select transistors of the ReRAM memory cell(s) to be erased are supplied with positive voltage pulses. The gates of the series-connected select transistors of the ReRAM memory cell(s) unselected for erasing are supplied with a voltage potential insufficient to turn them on.