公开(公告)号：US09973202B2

公开(公告)日：2018-05-15

申请号：US15714772

申请日：2017-09-25

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kentaro Yoshioka ,  Masanori Furuta ,  Hiroshi Kubota

IPC: H03M1/38 ,  H03M1/46

CPC classification number: H03M1/462 ,  H03M1/0656 ,  H03M1/466 ,  H03M1/468 ,  H03M1/804

Abstract: A successive approximation register (SAR) analog-to-digital converter includes a first capacitance digital-to-analog converter (CDAC), a first comparator configured to compare a voltage of an output signal from the first CDAC with a reference voltage, a first SAR circuit configured to control the first CDAC based on an output of the first comparator, a second CDAC to which the output signal from the first CDAC is input, a second comparator configured to compare a voltage of an output signal from the second CDAC with a reference voltage, a second SAR circuit configured to control the second CDAC based on an output of the second comparator and generate a digital signal representing a residual voltage of the output signal of the first CDAC, and a feedback circuit configured to delay the digital signal, generate a residual signal from the delayed digital signal, and output the residual signal to the first CDAC.

公开(公告)号：US09240847B2

公开(公告)日：2016-01-19

申请号：US14401597

申请日：2013-03-25

Applicant: Robert Bosch GmbH

Inventor： Thomas Wuchert ,  Matthias Kalisch

IPC: H04L7/00 ,  H04B15/00 ,  H03M1/06 ,  G01D3/032 ,  H04L7/02 ,  H04L27/10 ,  H03M1/12

CPC classification number: H04B15/00 ,  G01D3/032 ,  H03M1/0656 ,  H03M1/1245 ,  H04L7/02 ,  H04L27/10

Abstract: A method is provided for suppressing interferences in a sampling process. The method includes the method step of sampling an analog useful signal at a sampling frequency f as well as determining whether an interference amplitude is present. In the presence of an interference amplitude, a stochastic shift of the chronologically equidistant sampling points in time, which are determined by the sampling frequency f, is carried out within a range [−Δt; +Δt] (21) around the equidistant sampling points in time, Δt being the maximum shift. Subsequently, a resampling of the analog useful signal is carried out. It is redetermined whether an interference amplitude is present. In the case of the continuous presence of an interference amplitude, a change in the absolute value of the maximum shift |Δt| is carried out and the process is restarted with the method step of stochastically shifting the sampling points in time.

Abstract translation: 提供了一种用于抑制采样过程中的干扰的方法。 该方法包括以采样频率f对模拟有用信号进行采样以及确定是否存在干扰幅度的方法步骤。 在存在干扰幅度的情况下，由采样频率f确定的时间上等距离采样点的随机偏移在[ - ＆Dgr; t]的范围内进行。 +＆Dgr; t]（21）在时间上的等距采样点周围，Dgr; t是最大偏移。 随后，进行模拟有用信号的再采样。 重新确定是否存在干扰幅度。 在连续存在干涉幅度的情况下，最大偏移|＆Dgr; t |的绝对值的变化 并且通过随时随地移动采样点的方法步骤重新开始处理。

公开(公告)号：US08917196B2

公开(公告)日：2014-12-23

申请号：US13882323

申请日：2012-12-27

Applicant: Asahi Kasei Microdevices Corporation

Inventor： Junya Nakanishi ,  Yutaka Nakanishi ,  Seiko Nakamoto

IPC: H03M1/00 ,  H03M1/12 ,  H03M1/06 ,  H03M1/66

CPC classification number: H03M1/1245 ,  H03M1/0656 ,  H03M1/12 ,  H03M1/1265 ,  H03M1/66

Abstract: An A/D converter comprising: a sampling circuit including a continuous section, a sampling and holding section for intermittently sampling an input signal based on an analog signal input from the continuous section to hold and transfer the sampled signal, and a digital section for outputting a signal transferred from the sampling and holding section as a digital signal; and a control circuit for supplying a clock signal in which jitter is not added to the continuous section and supplying a clock signal in which the jitter is added to the sampling and holding section.

Abstract translation: 一种A / D转换器，包括：采样电路，包括连续部分，采样和保持部分，用于基于从连续部分输入的模拟信号间歇地采样输入信号，以保持和传送采样信号;以及数字部分，用于输出 从采样保持部分传送的信号作为数字信号; 以及控制电路，用于提供不连续抖动的时钟信号，并将提供抖动的时钟信号提供给采样保持部。

公开(公告)号：US20120206286A1

公开(公告)日：2012-08-16

申请号：US13389663

申请日：2010-08-09

Applicant: Oystein Moldsvor

Inventor： Oystein Moldsvor

IPC: H03M1/12

CPC classification number: H03M1/0845 ,  H03M1/0643 ,  H03M1/0656 ,  H03M1/12 ,  H03M1/1255

Abstract: An analog-to-digital-converter includes an input signal connector, an output signal port, two or more sub-ADCs, and a digital signal processing block. The result from each sub-ADC is used by the digital signal processing block to output data with increased performance.

Abstract translation: 模数转换器包括输入信号连接器，输出信号端口，两个或多个子ADC，以及数字信号处理块。 每个子ADC的结果由数字信号处理块用于以更高的性能输出数据。

公开(公告)号：US07869976B2

公开(公告)日：2011-01-11

申请号：US12317221

申请日：2008-12-18

Applicant: Kim Brøndum Larsen ,  Mogens Lønberg Lau ,  Flemming Buus Bendixen

Inventor： Kim Brøndum Larsen ,  Mogens Lønberg Lau ,  Flemming Buus Bendixen

IPC: G06F15/00

CPC classification number: H02P9/007 ,  G01D5/24461 ,  G01D5/24476 ,  H02P2101/15 ,  H03M1/0656 ,  H03M1/24 ,  H03M1/645

Abstract: An electric power generator system is provided with improved power efficiency due to a reduced sensitivity to errors in the sensing of angular rotor position. The system includes a power generator with a rotor, and a position encoder connected to sense angular position of the rotor and to generate a position signal accordingly. A processor receives the position signal, calculates an angular position in response, calculates an estimated angular position based on earlier received position signals, and finally generates a processed angular position based on the calculated angular position and the estimated angular position. This processed angular position is a more reliable measure of the rotor position, reducing the influence of short-term errors in the position signal, allowing normal wind turbine operation during temporary position encoder failure, and allowing an orderly shutdown during complete position encoder failure.

Abstract translation: 发电机系统由于对角度转子位置的检测中的误差的敏感性降低而具有改善的功率效率。 该系统包括具有转子的发电机和连接到感测转子的角位置并相应地产生位置信号的位置编码器。 处理器接收位置信号，计算响应中的角度位置，基于先前接收到的位置信号计算估计的角度位置，并且基于计算的角位置和估计的角位置最终生成经处理的角位置。 该处理的角位置是对转子位置的更可靠的测量，减少位置信号中的短期误差的影响，允许临时位置编码器故障期间的正常风力涡轮机运行，并允许在完成位置编码器故障期间有序关闭。

公开(公告)号：US07764208B2

公开(公告)日：2010-07-27

申请号：US12275871

申请日：2008-11-21

Applicant: Pietro Mario Adduci ,  Edoardo Botti ,  Giovanni Gonano

Inventor： Pietro Mario Adduci ,  Edoardo Botti ,  Giovanni Gonano

IPC: H03M1/20

CPC classification number: H03M1/0656 ,  H03L7/0805 ,  H03L7/0995 ,  H03L7/18 ,  H03M1/66

Abstract: A process and apparatus for generating an output signal whose frequency varies according to a modulation scheme, the process including the steps of providing a dither generator for receiving a first input signal representative of a clock frequency and for generating, according to the modulation scheme, a dithered output signal representative of the first signal at a dithered frequency; providing a DSP for receiving the following input signals: the signal at the dithered frequency and a second signal representative of a clock frequency, the DSP adapted to generate a processed output signal representative of the maximum frequency of the second signal; wherein the modulation scheme has a periodic ultrasonic modulating wave.

Abstract translation: 一种用于产生其频率根据调制方案而变化的输出信号的处理和装置，所述处理包括以下步骤：提供用于接收表示时钟频率的第一输入信号的抖动发生器，并根据调制方案生成 以抖动​​频率表示第一信号的抖动输出信号; 提供用于接收以下输入信号的DSP：处于抖动频率的信号和表示时钟频率的第二信号，DSP适于产生表示第二信号的最大频率的经处理的输出信号; 其中调制方案具有周期性超声波调制波。

公开(公告)号：US20090058697A1

公开(公告)日：2009-03-05

申请号：US11684572

申请日：2007-03-09

Applicant: Arne Aas ,  Gunnar Gangstoe ,  Torgeir Fenheim

Inventor： Arne Aas ,  Gunnar Gangstoe ,  Torgeir Fenheim

IPC: H03M1/10 ,  H03M1/12

CPC classification number: G01R19/0092 ,  G01R19/2509 ,  H03M1/0607 ,  H03M1/0656 ,  H03M3/34 ,  H03M3/356

Abstract: A method and system utilized with an analog to digital converter is disclosed. The method and system comprise providing a first conversion on an input signal. In the first conversion, an offset error is added to the input signal to provide a first result. The method and system further includes providing a second conversion on the input signal. In the second conversion, an offset error is subtracted from the input signal to provide a second result. The first and second results are then combined to substantially remove the offset error. A system and method in accordance with the present invention compensates for the accumulated offset error over many samples, thereby achieving much higher accuracy in the offset error compensation.

Abstract translation: 公开了一种使用模数转换器的方法和系统。 该方法和系统包括在输入信号上提供第一转换。 在第一次转换中，偏移误差被添加到输入信号以提供第一结果。 该方法和系统还包括对输入信号提供第二转换。 在第二转换中，从输入信号中减去偏移误差以提供第二结果。 然后组合第一和第二结果以基本上去除偏移误差。 根据本发明的系统和方法补偿多个样本上的累积偏移误差，从而在偏移误差补偿中获得高得多的精度。

公开(公告)号：US20070146191A1

公开(公告)日：2007-06-28

申请号：US11585077

申请日：2006-10-24

Applicant: Shigeyasu Iwata ,  Takeshi Ueno ,  Toshifumi Yamamoto

Inventor： Shigeyasu Iwata ,  Takeshi Ueno ,  Toshifumi Yamamoto

IPC: H03M1/12

CPC classification number: H03M1/0656 ,  H03M1/0682 ,  H03M1/205 ,  H03M1/365

Abstract: An analog-to-digital converter includes a track hold circuit, a reference voltage generating circuit, a switched capacitor circuit, a preamplifier that amplifies a voltage held by the switched capacitor circuit, a comparator that generates a logic level corresponding to an output from the preamplifier, and an encoder that converts the logic level into a binary code (n-bit digital output). If capacitors constituting the switched capacitor circuit are charged and the charges in these capacitors then vary, each capacitor is recharged by an amount corresponding to the particular variation.

Abstract translation: 模数转换器包括轨道保持电路，参考电压产生电路，开关电容器电路，放大由开关电容电路保持的电压的前置放大器，产生与来自所述开关电容器的输出相对应的逻辑电平的比较器 前置放大器和将逻辑电平转换为二进制码（n位数字输出）的编码器。 如果构成开关电容器电路的电容器被充电，并且这些电容器中的电荷然后变化，则每个电容器对与特定变化相对应的量进行充电。

公开(公告)号：US20050270193A1

公开(公告)日：2005-12-08

申请号：US11127738

申请日：2005-05-12

Applicant: Victor Dias

Inventor： Victor Dias

IPC: H03M1/06 ,  H03M1/66 ,  H03M3/00 ,  H03M7/00

CPC classification number: H03M1/0656 ,  H03M1/66 ,  H03M3/336 ,  H03M3/502

Abstract: Method and device for reducing the signal images at the output of a digital/analogue converter. In a method for reducing the signal images at the output of a digital/analogue converter, a frequency hopping clock generator provides a digital data signal whose data rate is varied according to a frequency hopping method. The digital data signal is converted into an analogue signal by a digital/analogue converter, the conversion clock being varied according to the frequency hopping method.

Abstract translation: 用于减少数字/模拟转换器输出端的信号图像的方法和装置。 在数字/模拟转换器的输出端减少信号图像的方法中，跳频时钟发生器提供数据数据信号，数据速率根据跳频方法而变化。 数字数据信号由数/模转换器转换为模拟信号，转换时钟根据跳频方式而变化。

公开(公告)号：US3740532A

公开(公告)日：1973-06-19

申请号：US3740532D

申请日：1971-05-25

Applicant: KUREHA CHEMICAL IND CO LTD

Inventor： ESCH R

IPC: G06F7/38 ,  H03K5/156 ,  H03K21/02 ,  H03M1/06 ,  H03M1/30

CPC classification number: H03M1/0656 ,  G06F7/38 ,  H03K5/156 ,  H03K21/02 ,  H03M1/30

Abstract: An arrangement for averaging the count received from a bidirectional pulse source such as a measuring machine position transducer is disclosed in which a relatively small capacity auxiliary counter is utilized in conjunction with a main counter, and includes means for causing the incoming pulses in either direction to bypass the auxiliary counter and pass to the main counter whenever the auxiliary counter is full in the direction of the incoming pulse. The count in the auxiliary counter is periodically sampled with the samples taken at regular intervals and an update signal reflecting the direction of the average count being added to the main counter and subtracted from the auxiliary counter at regular intervals.

Abstract translation: 公开了一种用于平均从双向脉冲源（例如测量机位置传感器）接收的计数的装置，其中相对较小容量的辅助计数器与主计数器结合使用，并且包括用于使输入脉冲沿任一方向 当辅助计数器在输入脉冲的方向满时，旁路辅助计数器并传递到主计数器。 辅助计数器中的计数是以规则的间隔采样的周期性采样的，并且反映平均计数方向的更新信号被加到主计数器上，并以规则的间隔从辅助计数器中减去。