公开(公告)号：US20190043956A1

公开(公告)日：2019-02-07

申请号：US16018304

申请日：2018-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L29/16 ,  H01L21/02

Abstract: A method of forming a semiconductor on a porous semiconductor structure. The method may include forming a stack, the stack includes (from bottom to top) a substrate, a base silicon layer, a thick silicon layer, and a thin silicon layer, where the thin silicon layer and the thick silicon layer are relaxed; converting the thick silicon layer into a porous silicon layer using a porousification process; and forming a III-V layer on the thin silicon layer, where the layer is relaxed, the thin silicon layer is strained, and the porous silicon layer is partially strained.

公开(公告)号：US20190043944A1

公开(公告)日：2019-02-07

申请号：US15667376

申请日：2017-08-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Matthew W. Stoker ,  Judson R. Holt ,  Timothy J. McArdle ,  Annie Lévesque

IPC: H01L29/06 ,  H01L27/108 ,  H01L21/02 ,  H01L29/49 ,  H01L29/423

Abstract: At least one method, apparatus and system disclosed herein involves forming increased surface regions within EPI structures. A fin on a semiconductor substrate is formed. On a top portion of the fin, an epitaxial (EPI) structure is formed. The EPI structure has a first EPI portion having a first material and a second EPI portion having a second material. The first and second EPI portions are separated by a first separation layer. A first cavity is formed within the EPI structure by removing a portion of the second material in the second portion. A first conductive material is deposited into the first cavity.

公开(公告)号：US10199479B2

公开(公告)日：2019-02-05

申请号：US14928681

申请日：2015-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gunter Grasshoff ,  Catherine Labelle

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321

Abstract: A method includes performing a first chemical mechanical polishing process to define a polished replacement gate structure having a dished upper surface, wherein the polished dished upper surface of the polished replacement gate structure has a substantially curved concave configuration. A gate cap layer is formed above the polished replacement gate structure, wherein a bottom surface of the gate cap layer corresponds to the polished dished upper surface of the polished replacement gate structure.

公开(公告)号：US10199378B2

公开(公告)日：2019-02-05

申请号：US15857202

申请日：2017-12-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Navneet Jain ,  Juhan Kim ,  Andy Nguyen ,  Mahbub Rashed

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L27/02 ,  H01L23/528 ,  H01L21/8238

Abstract: Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.

公开(公告)号：US10198550B2

公开(公告)日：2019-02-05

申请号：US15478377

申请日：2017-04-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andrey A. Lutich

IPC: G06F17/50 ,  G03F1/36

Abstract: Embodiments of the disclosure provide a method including: identifying a target feature in an integrated circuit (IC) layout not represented in a library, the library including a plurality of sub-resolution assist feature (SRAF) usefulness maps corresponding to a plurality of features and SRAFs in the IC layout; generating a usefulness map for the target feature with an artificial neural network (ANN), the generating being based on the target feature and the plurality of SRAF usefulness maps in the library; adding the target feature and the generated usefulness map to the library; selecting an SRAF insertion site for the target feature based on the generated usefulness map; and inserting an SRAF for the target feature into the IC layout at the selected SRAF insertion site.

公开(公告)号：US20190035791A1

公开(公告)日：2019-01-31

申请号：US16111263

申请日：2018-08-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Jerome Ciavatti ,  Rinus Tek Po Lee

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L27/10814 ,  B82Y10/00 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L27/1248 ,  H01L29/0676 ,  H01L29/1037 ,  H01L29/42376 ,  H01L29/66439 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/78642

Abstract: Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.

公开(公告)号：US20190035780A1

公开(公告)日：2019-01-31

申请号：US16147303

申请日：2018-09-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chien-Hsin Lee ,  Manjunatha Prabhu ,  Mahadeva Iyer Natarajan

IPC: H01L27/02 ,  H01L23/535 ,  H01L21/768 ,  H01L29/417 ,  G05B19/4097

CPC classification number: H01L27/0288 ,  G05B19/4097 ,  G05B2219/45031 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/4175

Abstract: Methods, apparatus, and systems relating to a MOSFET with ESD resistance, specifically, to a semiconductor device comprising a field-effect transistor (FET) comprising a gate, a source, and a drain, all extending parallel to each other in a first direction; at least one source electrostatic discharge (ESD) protection circuit; a source terminal disposed above and in electrical contact with the at least one source ESD protection circuit, wherein the source terminal extends in the first direction; at least one drain ESD protection circuit; and a drain terminal disposed above and in electrical contact with the at least one drain ESD protection circuit, wherein the drain terminal extends in the first direction.

公开(公告)号：US20190035692A1

公开(公告)日：2019-01-31

申请号：US15658524

申请日：2017-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Lars W. Liebmann ,  Bipul C. Paul ,  Daniel Chanemougame ,  Nigel G. Cave

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method includes forming a first gate structure above a first region of a semiconducting substrate. A first sidewall spacer is formed adjacent the first gate structure. The first gate structure and the first sidewall spacer are recessed to define a first gate contact cavity. A second sidewall spacer is formed in the first gate contact cavity. A first conductive gate contact is formed in the first gate contact cavity. The second sidewall spacer is removed to define a first spacer cavity. A conductive material is formed in the first spacer cavity to form a first conductive spacer contacting the first conductive gate contact.

公开(公告)号：US10192786B2

公开(公告)日：2019-01-29

申请号：US15590195

申请日：2017-05-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Jinping Liu

IPC: H01L21/8234 ,  H01L29/417 ,  H01L21/02 ,  H01L27/088

Abstract: A multi-masking process is used to form semiconductor fin arrays having a controlled and variable fin pitch and fin critical dimension within different arrays. A layer of curable silicon nitride is incorporated into a patterning architecture, patterned to form an etch mask, and locally cured to further modify the etch mask geometry. The use of cured and uncured structures facilitate the tuning of the resultant fin geometry.

公开(公告)号：US10192779B1

公开(公告)日：2019-01-29

申请号：US15935606

申请日：2018-03-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Siva P. Adusumilli

IPC: H01L21/763 ,  H01L29/06 ,  H01L27/12 ,  H01L27/06 ,  H01L21/762 ,  H01L21/324 ,  H01L21/84 ,  H01L21/265 ,  H01L21/02

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A non-single-crystal layer has a first section arranged beneath the trench isolation regions and a second section arranged beneath the active device region. The first section of the non-single-crystal layer has a first width in a vertical direction. The second section of the non-single-crystal layer has a second width in the vertical direction that is less than the first width of the first section of the non-single-crystal layer.