公开(公告)号：US09042504B2

公开(公告)日：2015-05-26

申请号：US14201778

申请日：2014-03-07

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Richard E. Perego ,  Craig E. Hampel

IPC: H04L7/00 ,  H04L7/10 ,  H04L25/02 ,  H04L25/12 ,  G11C7/04 ,  H04L7/033

CPC classification number: H04L7/0016 ,  G11C7/04 ,  G11C2207/2254 ,  H04L7/0087 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/0292 ,  H04L25/12

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

Abstract translation: 方法和系统提供在通信信道的正常操作期间不时地执行校准周期。 校准周期包括将来自发射机的正常数据源解耦，并在其位置提供校准模式。 使用第二组件上的接收器从通信链路接收校准模式。 响应于所接收的校准模式来确定通信信道的参数的校准值。 校准周期中涉及的步骤可以重新排序以考虑通信信道的利用模式。 对于双向链路，执行校准周期，其包括将接收到的校准模式存储在第二组件上的步骤，以及将这些校准模式重新发送回第一组件以用于调整第一组件上的通道的参数。

公开(公告)号：US20150131388A1

公开(公告)日：2015-05-14

申请号：US14538524

申请日：2014-11-11

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G11C11/408 ,  G11C11/4093 ,  G11C5/04

CPC classification number: G11C11/4082 ,  G06F12/06 ,  G06F13/1673 ,  G06F13/1684 ,  G11C5/04 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

公开(公告)号：US20150103610A1

公开(公告)日：2015-04-16

申请号：US14573323

申请日：2014-12-17

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C11/406 ,  G11C11/4074

CPC classification number: G11C11/40615 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/022 ,  G11C29/028

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

Abstract translation: 在一个实施例中，存储器设备包括存储器核心和用于接收命令和数据的输入接收器。 存储器装置还包括寄存器，用于存储指示输入接收器的子集是否响应于控制信号掉电的值。 存储器控制器将命令和数据发送到存储器件。 存储器控制器还发送该值以指示存储器件的输入接收器的子集是否响应于控制信号掉电。 此外，响应于自我新命令，存储装置延迟进入自刷新操作，直到接收到接收到自刷新命令后接收的控制信号为止。

公开(公告)号：US09007862B2

公开(公告)日：2015-04-14

申请号：US13938130

申请日：2013-07-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness ,  Ian P. Shaeffer ,  James E. Harris

IPC: G11C7/00 ,  G11C11/406 ,  G11C7/10

CPC classification number: G11C7/00 ,  G11C7/1009 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40622

Abstract: Components of a memory system, such as a memory controller and a memory device, that reduce delay in exiting self-refresh mode by controlling the refresh timing of the memory device. The memory device includes a memory core. An interface circuit of the memory device receives an external refresh signal indicating an intermittent refresh event. A refresh circuit of the memory device generates an internal refresh signal indicating an internal refresh event of the memory device. A refresh control circuit of the memory device performs a refresh operation on a portion of the memory core responsive to the internal refresh event, at a time relative to the intermittent refresh event indicated by the external refresh signal.

Abstract translation: 诸如存储器控制器和存储器设备的存储器系统的组件通过控制存储器件的刷新定时来减少退出自刷新模式的延迟。 存储器件包括存储器核。 存储装置的接口电路接收指示间歇刷新事件的外部刷新信号。 存储器件的刷新电路产生指示存储器件的内部刷新事件的内部刷新信号。 存储器件的刷新控制电路响应于内部刷新事件，在相对于由外部刷新信号指示的间歇刷新事件的时间，对存储器核心的一部分执行刷新操作。

公开(公告)号：US08982598B2

公开(公告)日：2015-03-17

申请号：US13865110

申请日：2013-04-17

Applicant: Rambus Inc.

Inventor： Paul Damian Franzon ,  Evan Lawrence Erickson ,  Thomas Vogelsang ,  Frederick A. Ware

IPC: G11C5/02 ,  G11C29/04 ,  G11C29/00

CPC classification number: G11C29/04 ,  G11C29/702 ,  G11C29/808

Abstract: A memory device includes a stack of circuit layers, each circuit layer having formed thereon a memory circuit configured to store data and a redundant resources circuit configured to provide redundant circuitry to correct defective circuitry on at least one memory circuit formed on at least one layer in the stack. The redundant resources circuit includes a partial bank of redundant memory cells, wherein an aggregation of the partial bank of redundant memory cells in each of the circuit layers of the stack includes at least one full bank of redundant memory cells and wherein the redundant resources circuit is configured to replace at least one defective bank of memory cells formed on any of the circuit layers in the stack with at least a portion of the partial bank of redundant memory cells formed on any of the circuit layers in the stack.

Abstract translation: 存储器件包括电路层堆叠，每个电路层上形成有存储器电路，其被配置为存储数据，冗余资源电路被配置为提供冗余电路以校正在至少一个层上形成的至少一个存储器电路上的有缺陷的电路 堆栈。 所述冗余资源电路包括冗余存储器单元的部分组，其中所述堆叠的每个电路层中的冗余存储器单元的部分组的聚集包括至少一个全部冗余存储器单元，并且其中所述冗余资源电路为 被配置为替换形成在堆叠中的任何电路层上的至少一个存储单元的至少一个有缺陷的存储单元组，其中所述冗余存储器单元的部分库的至少一部分形成在堆叠中的任何电路层上。

公开(公告)号：US20140344546A1

公开(公告)日：2014-11-20

申请号：US14449610

申请日：2014-08-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Craig E. Hampel ,  Wayne S. Richardson ,  Chad A. Bellows ,  Lawrence Lai

IPC: G06F3/06 ,  G11C7/10

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0673 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/22 ,  G11C8/06 ,  G11C11/4076 ,  G11C11/4097

Abstract: A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

Abstract translation: 微线程存储器件。 提供了多个存储体，每个存储体包括多行存储单元并且具有访问限制，因为至少最小访问时间间隔必须在对存储单元的给定行的连续访问之间发生。 提供传送控制电路以响应于第一存储器访问请求在多个存储体和外部信号路径之间传送第一数据量，第一数据量小于外部信号路径带宽和 最小访问时间间隔。

公开(公告)号：US20140334236A1

公开(公告)日：2014-11-13

申请号：US14445014

申请日：2014-07-28

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Frederick A. Ware

IPC: G11C11/4076

CPC classification number: G11C11/4076 ,  G06F1/04 ,  G06F13/4243 ,  G11C7/04 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  H04L7/0008 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

Abstract translation: 公开了一种操作存储器控制器的方法。 该方法包括通过至少两个并行数据链路中的每一个将数据信号发送到存储器设备。 在第一专用链路上将定时信号发送到存储设备。 定时信号与数据信号具有固定的相位关系。 数据选通信号被驱动到第二专用链路上的存储器件。 从存储器件接收相位信息。 相位信息在存储器件内部产生，并且基于定时信号与内部分布在存储器件内的数据选通信号的版本之间的比较。 基于接收的相位信息，相对于定时信号调整数据选通信号的相位。

公开(公告)号：US20140329359A1

公开(公告)日：2014-11-06

申请号：US14272295

申请日：2014-05-07

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Ian P. Shaeffer

IPC: H01L21/768

CPC classification number: H01L21/768 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/00

Abstract: Multiple devices, including a first device and a second device, have operational circuitry and opposing first and second surfaces. First and second electrical contacts are formed at the first surface, while a third electrical contact is formed at the second surface opposite the first electrical contact. The first electrical contact is electrically connected to the operational circuitry, and the second electrical contact is electrically connected to the third electrical contact. The first device and the second device are subsequently stacked such that the first surface of the second device is located adjacent the second surface of the first device such that the first electrical contact of the second device is aligned with the third electrical contact of the first device. The first electrical contact of the second device is electrically connected to the third electrical contact of the first device.

Abstract translation: 包括第一设备和第二设备的多个设备具有操作电路和相对的第一和第二表面。 第一和第二电触点形成在第一表面处，而在与第一电触头相对的第二表面处形成第三电接触。 第一电触头电连接到操作电路，并且第二电触头电连接到第三电触头。 随后堆叠第一装置和第二装置，使得第二装置的第一表面位于第一装置的第二表面附近，使得第二装置的第一电触点与第一装置的第三电触点对准 。 第二器件的第一电接触电连接到第一器件的第三电接触件。

公开(公告)号：US20140321186A1

公开(公告)日：2014-10-30

申请号：US14319544

申请日：2014-06-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Paul D. Franzon

IPC: G11C5/02 ,  H01L23/538 ,  G11C29/00

CPC classification number: G11C5/02 ,  G11C7/22 ,  G11C11/4076 ,  G11C29/80 ,  G11C29/808 ,  G11C2213/71 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip. The second integrated circuit memory chip has second storage locations. Redundant storage is provided including a first storage area dedicated to storing failure address information of failure address locations in the first or second integrated circuit memory chips. The redundant storage includes a second storage area dedicated to storing data corresponding to the failure address locations. Matching logic matches incoming data transfer addresses to the stored failure address information.

Abstract translation: 公开了一种堆叠存储器，其包括具有第一存储位置的第一集成电路存储器芯片和与第一集成电路存储器芯片堆叠关系地设置的第二集成电路存储器芯片。 第二集成电路存储器芯片具有第二存储位置。 提供了冗余存储器，其包括专用于存储第一或第二集成电路存储器芯片中的故障地址位置的故障地址信息的第一存储区域。 冗余存储器包括专用于存储对应于故障地址位置的数据的第二存储区域。 匹配逻辑将输入的数据传输地址与存储的故障地址信息进行匹配。

公开(公告)号：US20140289574A1

公开(公告)日：2014-09-25

申请号：US14353401

申请日：2012-10-19

Applicant: RAMBUS INC.

Inventor： Ely Tsern ,  Frederick A. Ware ,  Suresh Rajan ,  Thomas Vogelsang

IPC: G11C29/24

CPC classification number: G06F11/1008 ,  G11C5/04 ,  G11C29/24 ,  G11C29/50016 ,  G11C2029/4402 ,  G11C2211/4061

Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

Abstract translation: 公开了一种在集成电路（IC）存储器件中的操作方法。 该方法包括以第一刷新率刷新IC存储设备中的第一组存储行。 测试每行的保留时间。 对被测试给定行的测试包括以比第一刷新率慢的第二刷新率刷新。 测试可以基于存储在给定行中的数据的访问请求而中断。