公开(公告)号：US20150084092A1

公开(公告)日：2015-03-26

申请号：US14496192

申请日：2014-09-25

Applicant: STMicroelectronics SA

Inventor： Pascal FONTENEAU

IPC: H01L31/111 ,  H01L31/18 ,  H01L31/11 ,  H01L31/0232

CPC classification number: H01L31/1113 ,  H01L27/1203 ,  H01L31/02019 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/105 ,  H01L31/11 ,  H01L31/18 ,  Y02E10/547

Abstract: An overvoltage protection component may be in a SOI layer, a portion of the SOI layer forming the core of an optical waveguide. This component may be made of semiconductor regions of different doping types and/or levels, at least one of these regions corresponding to at least a portion of the waveguide core.

Abstract translation: 过电压保护组件可以在SOI层中，SOI层的一部分形成光波导的核心。 该组件可以由不同掺杂类型和/或电平的半导体区域制成，这些区域中的至少一个对应于波导芯的至少一部分。

公开(公告)号：US08962399B2

公开(公告)日：2015-02-24

申请号：US14177593

申请日：2014-02-11

Applicant: Commissariat a l'Energie Atomique et aux Ene Alt ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Maud Vinet ,  Yves Morand ,  Heimanu Niebojewski

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/762

CPC classification number: H01L29/66477 ,  H01L21/02236 ,  H01L21/02667 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/7624 ,  H01L21/76248 ,  H01L21/76272 ,  H01L21/76278 ,  H01L21/84 ,  H01L27/1207

Abstract: A method is provided for producing a semiconductor layer having at least two different thicknesses from a stack of the semiconductor on insulator type including at least one substrate on which an insulating layer and a first semiconductor layer are successively disposed, the method including etching the first layer so that said layer is continuous and includes at least one first region having a thickness less than that of at least one second region; oxidizing the first layer to form an electrically insulating oxide film on a surface thereof so that, in the first region, the oxide film extends as far as the insulating layer; partly removing the oxide film to bare the first layer outside the first region; forming a second semiconductor layer on the stack, to form, with the first layer, a third continuous semiconductor layer having a different thickness than that of the first and second regions.

Abstract translation: 提供一种用于制造半导体层的半导体层的方法，所述半导体层具有至少两个不同厚度的绝缘体上的半导体层，包括至少一个其上连续设置有绝缘层和第一半导体层的基板，所述方法包括蚀刻第一层 使得所述层是连续的并且包括至少一个具有小于至少一个第二区域的厚度的第一区域; 氧化第一层以在其表面上形成电绝缘氧化膜，使得在第一区域中，氧化膜延伸至绝缘层; 部分地除去氧化膜以露出第一区域外的第一层; 在所述堆叠上形成第二半导体层，以与所述第一层形成具有与所述第一和第二区域的厚度不同的厚度的第三连续半导体层。

公开(公告)号：US20150050001A1

公开(公告)日：2015-02-19

申请号：US14527249

申请日：2014-10-29

Applicant: STMicroelectronics SA

Inventor： Sébastien Pruvost ,  Frederic Gianesello

IPC: H01P3/00

CPC classification number: H01P3/003 ,  H01P3/006 ,  H01P3/082

Abstract: A coplanar waveguide electronic device is formed on a substrate. The waveguide includes a signal ribbon and a ground plane. The signal ribbon is formed of two or more signal lines of a same level of metallization that are electrically connected together. The ground plane is formed of an electrically conducting material which includes rows of holes.

Abstract translation: 在基板上形成共面波导电子器件。 波导包括信号带和接地平面。 信号带由两个或更多个电连接在一起的相同金属化水平的信号线形成。 接地平面由导电材料形成，其包括一排孔。

公开(公告)号：US20150044828A1

公开(公告)日：2015-02-12

申请号：US14453800

申请日：2014-08-07

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS SA

Inventor： Perrine BATUDE ,  Frederic Mazen ,  Benoit Sklenard

IPC: H01L29/786 ,  H01L21/324 ,  H01L21/265

CPC classification number: H01L29/78603 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/1045 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78654

Abstract: A Method for manufacturing a transistor comprising: a) amorphization and doping, by means of one or more localised implantation(s), of given regions of source and drain blocks based on crystalline semi-conductor material lying on an insulating layer of a semi-conductor on insulator substrate, the implantation(s) being carried out so as to conserve at the surface of said blocks zones of crystalline semi-conductor material on the regions of amorphous semi-conductor material, b) recrystallization of at least one portion of said given regions.

Abstract translation: 一种用于制造晶体管的方法，包括：a）通过位于半导体绝缘层上的晶体半导体材料的源极和漏极区域的给定区域的一个或多个局部注入来非晶化和掺杂， 导体绝缘体衬底上，进行注入以便在非晶半导体材料区域上的结晶半导体材料的所述块区的表面处保存，b）至少一部分所述 给定地区。

公开(公告)号：US20140370668A1

公开(公告)日：2014-12-18

申请号：US14177592

申请日：2014-02-11

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (Crolles 2) SAS

Inventor： Heimanu NIEBOJEWSKI ,  Yves MORAND ,  Maud VINET

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L21/28123 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02645 ,  H01L21/02667 ,  H01L21/76205 ,  H01L21/7624 ,  H01L21/76248 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78603

Abstract: The invention relates to a method for manufacturing a transistor comprising the preparation of a stack of layers of the semiconductor on insulator type comprising at least one substrate on which an insulating layer and an initial semiconductor layer are successively disposed. The method includes the formation of at least one oxide pad extending from a top face of the insulating layer, the formation of an additional layer made from semiconductor material covering the oxide pad and intended to form a channel for the transistor, the formation of a gate stack above the oxide pad, and the formation of a source and drain on either side of the gate stack.

Abstract translation: 本发明涉及一种晶体管的制造方法，其包括制备绝缘体上半导体层的一叠叠层，其中至少一个衬底上依次配置绝缘层和初始半导体层。 该方法包括形成从绝缘层的顶面延伸的至少一个氧化物焊盘，形成由半导体材料制成的附加层，该半导体材料覆盖氧化物焊盘并且旨在形成用于晶体管的沟道，形成栅极 堆叠在氧化物垫的上方，并且在栅极堆叠的任一侧上形成源极和漏极。

公开(公告)号：US20140359332A1

公开(公告)日：2014-12-04

申请号：US14279514

申请日：2014-05-16

Applicant: STMicroelectronics SA

Inventor： Fabien TODESCHINI ,  Christophe PLANAT ,  Patrizia MILAZZO ,  Salvatore TRICOMI ,  Séverin TROCHUT ,  Pascal URARD

IPC: G06F1/32

CPC classification number: G06F1/3293 ,  H02J7/35

Abstract: A power management circuit including, between a first terminal intended to be connected to an electric power generation source and a second terminal intended to be connected to a load to be powered, a linear regulator and a circuit capable of activating the linear regulator when the power supplied by said source is greater than a first threshold.

Abstract translation: 一种电力管理电路，包括在要连接到发电源的第一端子和旨在连接到要供电的负载的第二端子之间，线性调节器和能够在所述电力的情况下启动所述线性调节器的电路 由所述源提供的大于第一阈值。

公开(公告)号：US20140349460A1

公开(公告)日：2014-11-27

申请号：US14270603

申请日：2014-05-06

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA

Inventor： Maud VINET ,  Laurent GRENOUILLET ,  Yves MORAND

IPC: H01L21/225 ,  H01L29/66 ,  H01L21/22

CPC classification number: H01L21/225 ,  H01L21/2225 ,  H01L21/823821 ,  H01L21/84 ,  H01L21/845 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618

Abstract: The substrate is provided with a first semiconducting area partially covered by a first masking pattern to define a protected surface and an open surface. A continuous layer of silicon-germanium is deposited in non-selective manner on the first semiconducting area and on the first gate pattern. The continuous silicon-germanium layer forms an interface with the first semiconducting area. A diffusion/condensation annealing is performed to make the germanium atoms diffuse from the silicon-germanium layer to the open surface of the first semiconducting area. The masking pattern is a gate stack of the transistor or is used to define the shape of the gate stack in an electrically insulating layer so as to form a self-aligned gate stack with the source and drain areas.

Abstract translation: 衬底设置有由第一掩模图案部分地覆盖以限定受保护表面和开放表面的第一半导体区域。 以非选择性方式在第一半导体区域和第一栅极图案上沉积连续的硅 - 锗层。 连续硅 - 锗层与第一半导体区形成界面。 进行扩散/缩合退火以使锗原子从硅 - 锗层扩散到第一半导体区域的开放表面。 掩模图案是晶体管的栅极堆叠，或者用于在电绝缘层中限定栅极堆叠的形状，以便形成具有源极和漏极区域的自对准栅极堆叠。

公开(公告)号：US08890728B2

公开(公告)日：2014-11-18

申请号：US14179993

申请日：2014-02-13

Applicant: STMicroelectronics SA

Inventor： Nicolas Le Dortz ,  Thierry Simon ,  Pascal Urard ,  Caroline Lelandais-Perrault

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/00

CPC classification number: H03M1/0624 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1225

Abstract: According to one mode of implementation, a method includes an estimation including on the one hand a correlation processing involving at least one part of the sampled signal, at least one part of at least one first signal gleaned from a derived signal representative of a temporal derivative of the sampled signal and at least one part of N partial filtered signals respectively representative of N weighted differences between N pairs of bracketing versions flanking the sampled signal, N being greater than or equal to 1. On the other hand, the estimation includes a matrix processing on the results of this correlation processing. Correction processing of the M−1 trains involves respectively M−1 second signals gleaned from the derived signal and the suite of M−1 shift coefficients.

Abstract translation: 根据一种实施方式，一种方法包括估计，其一方面包括涉及采样信号的至少一部分的相关处理，从代表时间导数的导出信号中收集的至少一个第一信号的至少一部分 的采样信号和N个部分滤波信号的至少一部分，分别代表在采样信号侧翼的N对包围版本之间的N个加权差，N大于或等于1.另一方面，估计包括矩阵 对该相关处理的结果进行处理。 M-1列车的校正处理涉及从派生信号和一组M-1移位系数收集的M-1个第二信号。

公开(公告)号：US20140319648A1

公开(公告)日：2014-10-30

申请号：US14261757

申请日：2014-04-25

Applicant: Commissariat a I'energie atomique et aux energies alternatives ,  STMicroelectronics SA

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L27/082 ,  H01L27/02

CPC classification number: H01L27/0248 ,  H01L27/0259 ,  H01L27/0296 ,  H01L27/1207

Abstract: An integrated circuit includes first and second electronic components, a buried UTBOX insulating layer, first and second ground planes plumb with the first and second electronic components, first and second wells, first and second biasing electrodes making contact with the first and second wells and with the first and second ground planes, a third electrode making contact with the first well, a first trench isolation separating the first and third electrodes and extending through the buried insulating layer as far as into the first well, and a second trench isolation that isolates the first electrode from the first component, and that does not extend as far as the interface between the first ground plane and the first well.

Abstract translation: 集成电路包括第一和第二电子元件，埋入的UTBOX绝缘层，第一和第二接地平面与第一和第二电子元件铅垂，第一和第二阱，与第一和第二阱接触的第一和第二偏压电极以及与 所述第一和第二接地平面，与所述第一阱接触的第三电极，分隔所述第一和第三电极并延伸穿过所述埋入绝缘层的第一沟槽隔离层，并且延伸到所述第一阱中;以及第二沟槽隔离， 第一电极，并且不延伸到第一接地平面和第一阱之间的界面。

公开(公告)号：US08873668B2

公开(公告)日：2014-10-28

申请号：US13651883

申请日：2012-10-15

Applicant: STMicroelectronics SA ,  STMicroelectronics (R&D) Ltd ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Andrew Ferris ,  Ignazio Antonino Urzi ,  Pascal Teissier

IPC: H04L25/34

CPC classification number: G06F13/423

Abstract: A circuit includes a first n-bit communications block and a second m-bit communications block. A controller is configured to control mode of operation for the first and second communications blocks. In a first mode, the first and second communications blocks function as a single communications block for n+m bit communications. In a second mode, the first and second communications blocks operate as substantially independent communications block for n bit communications and m bit communications.

Abstract translation: 电路包括第一n比特通信块和第二m比特通信块。 控制器被配置为控制第一和第二通信块的操作模式。 在第一模式中，第一和第二通信块用作n + m位通信的单个通信块。 在第二模式中，第一和第二通信块作为用于n位通信和m位通信的基本上独立的通信块来操作。