公开(公告)号：US09698771B1

公开(公告)日：2017-07-04

申请号：US15203461

申请日：2016-07-06

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla

IPC: H03K17/22 ,  H03K5/19 ,  H03K19/20

CPC classification number: H03K17/223 ,  G01R31/2832 ,  G06F1/24 ,  G06F1/30 ,  H03K5/19 ,  H03K17/22 ,  H03K19/20

Abstract: A power management circuit includes both a power on reset (POR) circuit and a voltage monitoring circuit. Explicit testing of these circuits is accomplished by controlling voltages applied to the circuits and monitoring an output signal responsive to a logical combination of outputs from the POR circuit and voltage monitoring circuit. The applied voltages are controlled with respect to timing of application, fixing of voltages and varying of voltages in a manner where a certain one of the circuits for explicit test is isolated with change in logic state of the output signal being indicative of operation of that isolated circuit.

公开(公告)号：US09696351B2

公开(公告)日：2017-07-04

申请号：US14585357

申请日：2014-12-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Daljeet Kumar ,  Tapas Nandy ,  Surendra Kumar

IPC: G01R19/04 ,  G01R19/25

CPC classification number: G01R19/04 ,  G01R19/2503

Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.

公开(公告)号：US09685867B2

公开(公告)日：2017-06-20

申请号：US14466666

申请日：2014-08-22

Applicant: STMicroelectronics International N.V.

Inventor： Bohumil Janik

IPC: H02M3/158

CPC classification number: H02M3/1582

Abstract: A method supplies power from a power source to a load. The method includes, in a first mode, electrically coupling a step-down converter node of a step-down converter alternately to the power source via a conductive bypass path that bypasses a step-up converter and to ground. The step-up converter has an input electrically coupled to the power source and the step-down converter has an output electrically coupled to the load. The method further includes, in a second mode, coupling the step-down converter node alternately to the power source via the bypass path and to an output of the step-up converter.

公开(公告)号：US09654252B2

公开(公告)日：2017-05-16

申请号：US14931331

申请日：2015-11-03

Applicant: STMicroelectronics International N.V.

Inventor： Achraf Dhayni ,  Hussein Hijazi

IPC: H04B7/04 ,  H04L1/06 ,  H04L1/00 ,  H04L25/03 ,  H04B7/0413

CPC classification number: H04L1/0054 ,  H04B7/0413 ,  H04L1/0631 ,  H04L25/03197 ,  H04L25/03242 ,  H04L25/03961 ,  H04L2025/03414 ,  H04L2025/0342 ,  H04L2025/03426

Abstract: A receiver estimates a vector of emitted symbols over a MIMO transmission channel which is emitted by emitting antennas. The receiver receives a vector of received symbols on receiving antennas. Estimation of the vector of emitted symbols is made by calculating a metric associated with a criterion for each vector of a subset of all possible vectors of emitted symbols and selecting an estimation for said vector of emitted symbols as the vector of emitted symbols among said subset which minimizes said metric.

公开(公告)号：US09621031B1

公开(公告)日：2017-04-11

申请号：US14923776

申请日：2015-10-27

Applicant: STMicroelectronics International N.V.

Inventor： Jitendra Jain ,  Ranajay Mallik

IPC: H05B37/04 ,  H02M3/04 ,  H05B33/08

CPC classification number: H02M3/04 ,  H05B33/0815 ,  H05B33/0827 ,  H05B33/0845 ,  H05B33/0887 ,  Y02B20/347

Abstract: A tunable voltage regulator has an output generating a variable voltage and an input that receives a trimming signal for controlling the output variable voltage. A current regulating circuit operates to regulate a current flowing through a load in response to the variable voltage. A control circuit senses the variable voltage and a drop voltage of the current regulating circuit, and determines whether the current regulating circuit has failed to regulate the current flowing through the load because the variable voltage is too low. In response thereto, the control circuit generates the trimming signal to set the variable voltage to a value sufficient for the current regulating circuit to successfully regulate the current flowing through the load.

公开(公告)号：US20170064321A1

公开(公告)日：2017-03-02

申请号：US14837051

申请日：2015-08-27

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Vindhyeshwari Kumar KASHYAP ,  Ajit Singh MOTRA ,  Mahesh Narain SHUKLA ,  Tarun SINGAL

IPC: H04N19/44 ,  H04N19/85 ,  H04N19/423 ,  H04N19/436

CPC classification number: H04N19/436 ,  H04N19/91

Abstract: A video decoder includes an input configured to receive a plurality of bins of a video digital data stream to be decoded. A processor and a memory associated therewith are configured to perform parallel decoding of multiple bins of the plurality of bins in a given processing cycle based upon a table containing delta range values and probable symbols.

Abstract translation: 视频解码器包括被配置为接收待解码的视频数字数据流的多个存储槽的输入。 处理器和与其相关联的存储器被配置为基于包含增量范围值和可能符号的表，在给定处理周期内执行多个箱中的多个箱的并行解码。

公开(公告)号：US09559665B2

公开(公告)日：2017-01-31

申请号：US14788714

申请日：2015-06-30

Applicant: STMicroelectronics International N.V.

Inventor： Amit Chhabra

IPC: H03K3/011 ,  G11C11/417 ,  H03K17/687 ,  H01L27/11

CPC classification number: H03K3/011 ,  G01K3/005 ,  G01K7/01 ,  G11C5/146 ,  G11C7/04 ,  G11C11/417 ,  H01L27/1104 ,  H03K17/687

Abstract: An integrated circuit die includes a plurality of transistors formed in a semiconductor substrate, the body regions of the transistors on a doped well region of the semiconductor substrate. A threshold detector selectively applies either a first voltage or second voltage to the doped well region based on whether the temperature of the semiconductor substrate is above or below a threshold temperature.

Abstract translation: 集成电路管芯包括形成在半导体衬底中的多个晶体管，在半导体衬底的掺杂阱区域上的晶体管的体区。 阈值检测器基于半导体衬底的温度是高于还是低于阈值温度来选择性地将第一电压或第二电压施加到掺杂阱区。

公开(公告)号：US20170005780A1

公开(公告)日：2017-01-05

申请号：US14788721

申请日：2015-06-30

Applicant: STMicroelectronics International N.V.

Inventor： Tapas Nandy ,  Nitin Gupta

IPC: H04L7/00

CPC classification number: H04L7/0008 ,  G06F1/10 ,  H04J3/0685 ,  H04L1/0026 ,  H04L5/00 ,  H04L7/02 ,  H04L7/027 ,  H04L7/033 ,  H04L7/0337

Abstract: A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.

Abstract translation: 源同步数据传输系统包括数据发送装置和数据接收装置。 专用数据线将数据信号从数据传输装置传送到数据接收装置。 专用时钟线将数据传输装置的调制时钟信号传送到数据接收装置。 数据传输装置包括：时钟数据驱动器，被配置为通过调制调制时钟信号的幅度将数据编码成调制时钟信号。 因此，源同步数据传输系统的时钟线携带时钟信号和附加数据。

公开(公告)号：US20170005568A1

公开(公告)日：2017-01-05

申请号：US14788704

申请日：2015-06-30

Applicant: STMicroelectronics International N.V.

Inventor： Saurabh Sona

IPC: H02M1/32 ,  H02P7/00 ,  H02M7/06

CPC classification number: H02M1/32 ,  H02H7/1222 ,  H02M5/458 ,  H02P7/00 ,  H02P29/0241

Abstract: An overvoltage protection device protects a half bridge circuit that receives a supply voltage. The overvoltage protection device includes a high speed overvoltage detector that receives the supply voltage, detects whether an overvoltage situation is present, and outputs an overvoltage signal that disables the switches of the half bridge circuit before the switches can be damaged by the overvoltage situation. With both the switches of the half-bridge disabled, the entire supply voltage appears across the two switches in series, by which each switch only receives half the entire voltage. Thus, by quickly disabling both switches of the half-bridge each switch only needs a maximum voltage rating equal to half the maximum voltage rating of the half bridge circuit as a whole. This leads to reduced size and cost for the switches of the half-bridge circuit.

Abstract translation: 过电压保护装置保护接收电源电压的半桥电路。 过压保护装置包括接收电源电压的高速过电压检测器，检测是否存在过电压情况，并且在开关可能被过电压情况损坏之前输出禁用半桥电路的开关的过电压信号。 由于半桥的两个开关都被禁用，整个电源电压出现在串联的两个开关中，每个开关仅接收整个电压的一半。 因此，通过快速禁用半桥的两个开关，每个开关仅需要等于半桥电路整体的最大额定电压的一半的最大额定电压。 这导致半桥电路的开关的尺寸和成本降低。

公开(公告)号：US09501980B2

公开(公告)日：2016-11-22

申请号：US13708604

申请日：2012-12-07

Applicant: STMicroelectronics International N.V.

Inventor： Nishant Omar ,  Ranajay Mallik

IPC: G09G5/10 ,  G09G3/34 ,  G06F3/14 ,  G09G3/32

CPC classification number: G09G3/3413 ,  G06F3/1446 ,  G09G3/32

Abstract: A display panel comprises an array of light elements arranged in n rows by m columns. At least one driver is configured to drive one of said columns and rows, wherein the or each driver is configured to drive each of said columns or said rows. A plurality of the display panels may be used together to form a display panel system.

Abstract translation: 显示面板包括以n行×m列排列的光元件阵列。 至少一个驱动器被配置为驱动所述列和行之一，其中所述或每个驱动器被配置为驱动所述列或所述行中的每一个。 多个显示面板可以一起使用以形成显示面板系统。