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    Flash Memory System Using Complementary Voltage Supplies
    324.
    发明申请
    Flash Memory System Using Complementary Voltage Supplies 审中-公开
    使用互补电压源的闪存系统

    公开(公告)号：US20170076809A1

    公开(公告)日：2017-03-16

    申请号：US15361473

    申请日：2016-11-27

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    IPC: G11C16/30 ,  H01L27/115 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26

    CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C8/08 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C2216/04 ,  H01L27/11521

    Abstract: A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. During the operations of program, read, or erase, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected memory cells.

    Abstract translation: 非易失性存储器件包括第一导电类型的半导体衬底。 非易失性存储单元的阵列位于半导体衬底中并且被布置成多个行和列。 每个存储单元包括第二导电类型的半导体衬底的表面上的第一区域和第二导电类型的半导体衬底的表面上的第二区域。 沟道区域在第一区域和第二区域之间。 字线覆盖在沟道区域的第一部分上，并且与第一区域绝缘，并且与第一区域相邻并且与第一区域几乎没有或没有重叠。 浮动栅极覆盖沟道区域的第二部分，与第一部分相邻，并与第二部分绝缘并与第二区域相邻。 耦合栅极覆盖浮栅。 位线连接到第一区域。 在程序，读取或擦除的操作期间，负电压可以被施加到所选择的或未选择的存储单元的字线和/或耦合门。

    Split Gate Non-volatile Memory Cell Having A Floating Gate, Word Line, Erase Gate, And Method Of Manufacturing
    325.
    发明申请
    Split Gate Non-volatile Memory Cell Having A Floating Gate, Word Line, Erase Gate, And Method Of Manufacturing 有权
    具有浮动门，字线，擦除门和制造方法的分离门非易失性存储单元

    公开(公告)号：US20170012049A1

    公开(公告)日：2017-01-12

    申请号：US15182527

    申请日：2016-06-14

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Mandana Tadayoni ,  Chien-Sheng Su ,  Nhan Do

    IPC: H01L27/115 ,  G11C16/26 ,  H01L29/788 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28

    CPC classification number: H01L27/11524 ,  G11C16/26 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883

    Abstract: A memory device including a silicon semiconductor substrate, spaced apart source and drain regions formed in the substrate with a channel region there between, and a conductive floating gate disposed over a first portion of the channel region and a first portion of the source region. An erase gate includes a first portion that is laterally adjacent to the floating gate and over the source region, and a second portion that extends up and over the floating gate. A conductive word line gate is disposed over a second portion of the channel region. The word line gate is disposed laterally adjacent to the floating gate and includes no portion disposed over the floating gate. The thickness of insulation separating the word line gate from the second portion of the channel region is less than that of insulation separating the floating gate from the erase gate.

    Abstract translation: 一种存储器件，包括硅半导体衬底，形成在衬底中的间隔开的源极和漏极区域，其间具有沟道区域，以及布置在沟道区域的第一部分和源极区域的第一部分之间的导电浮动栅极。 擦除栅极包括横向邻近浮动栅极并在源极区域上方的第一部分，以及在浮动栅极上方和上方延伸的第二部分。 导电字线栅极设置在沟道区域的第二部分上。 字线栅极横向地布置在浮动栅极附近，并且不包括设置在浮动栅极上的部分。 将字线栅极与沟道区域的第二部分分开的绝缘层的厚度小于将浮栅与擦除栅极分开的绝缘层的厚度。

    Array Of Non-volatile Memory Cells With ROM Cells
    327.
    发明申请
    Array Of Non-volatile Memory Cells With ROM Cells 有权
    具有ROM单元的非易失性存储单元阵列

    公开(公告)号：US20160254269A1

    公开(公告)日：2016-09-01

    申请号：US14639063

    申请日：2015-03-04

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Jinho Kim ,  Vipin Tiwari ,  Nhan Do ,  Xian Liu ,  Xiaozhou Qian ,  Ning Bai ,  Kai Man Yue

    IPC: H01L27/115 ,  H01L29/788 ,  H01L29/423

    CPC classification number: H01L27/11524 ,  H01L23/57 ,  H01L27/11226 ,  H01L27/11233 ,  H01L27/11253 ,  H01L27/11519 ,  H01L29/42328 ,  H01L29/788 ,  H01L29/7881

    Abstract: A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.

    Abstract translation: 一种存储器件，其包括多个ROM单元，每个ROM单元具有形成在衬底中的间隔开的源极和漏极区域，其间具有沟道区域，设置在沟道区域的第一部分上方并与沟道区域的第一部分绝缘的第一栅极， 与沟道区的第二部分绝缘，以及在多个ROM单元上延伸的导电线。 导电线电耦合到ROM单元的第一子组的漏极区域，并且不电耦合到ROM单元的第二子组的漏极区域。 或者，ROM单元的第一子组各自包括沟道区域中的较高电压阈值注入区域，而ROM单元的第二子组每个在沟道区域中都缺少任何较高电压阈值注入区域。

    High Density Split-Gate Memory Cell
    328.
    发明申请
    High Density Split-Gate Memory Cell 审中-公开
    高密度分离栅极存储单元

    公开(公告)号：US20160217849A1

    公开(公告)日：2016-07-28

    申请号：US15002302

    申请日：2016-01-20

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Nhan Do ,  Xian Liu ,  Vipin Tiwari ,  Hieu Van Tran

    IPC: G11C11/419 ,  G11C16/14 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788

    CPC classification number: G11C11/419 ,  G11C16/0458 ,  G11C16/14 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7887

    Abstract: A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer. First trenches are formed through third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer, leaving side portions of the first conductive layer exposed. A fourth insulation layer is formed at the bottom of the first trenches that extends along the exposed portions of the first conductive layer. The first trenches are filled with conductive material. Second trenches are formed through the third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer. Drain regions are formed in the substrate under the second trenches. A pair of memory cells results, with a single continuous channel region extending between drain regions for the pair of memory cells.

    Abstract translation: 一种形成存储器件的方法，包括在衬底上形成第一绝缘层，第一导电层，第二绝缘层，第二导电层，第三绝缘层。 第一沟槽通过第三绝缘层，第二导电层，第二绝缘层和第一导电层形成，从而使第一导电层的侧面部分露出。 第一绝缘层形成在沿第一导电层的暴露部分延伸的第一沟槽的底部。 第一个沟槽填充有导电材料。 第二沟槽通过第三绝缘层，第二导电层，第二绝缘层和第一导电层形成。 在第二沟槽下的衬底中形成漏区。 导致一对存储单元，其中单个连续沟道区域在用于该对存储单元的漏极区域之间延伸。

    Split Gate Non-volatile Flash Memory Cell Having Metal Gates And Method Of Making Same
    329.
    发明申请
    Split Gate Non-volatile Flash Memory Cell Having Metal Gates And Method Of Making Same 有权
    具有金属门的分流门非易失性闪存单元及其制作方法

    公开(公告)号：US20160197088A1

    公开(公告)日：2016-07-07

    申请号：US14589650

    申请日：2015-01-05

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chun-Ming Chen ,  Man-Tang Wu ,  Jeng-Wei Yang ,  Chien-Sheng Su

    IPC: H01L27/115 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L29/788 ,  H01L29/423 ,  H01L29/45

    CPC classification number: H01L27/11521 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/511 ,  H01L29/517 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

    Abstract: A non-volatile memory cell includes a substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type spaced apart from the first region, forming a channel region therebetween. A floating gate is disposed over and insulated from a first portion of the channel region which is adjacent the first region. A select gate is disposed over a second portion of the channel region adjacent to the second region, the select gate being formed of a metal material and being insulated from the second portion of the channel region by a layer of silicon dioxide and a layer of high K insulating material. A control gate is disposed over and insulated from the floating gate. An erase gate is disposed over and insulated from the first region, and disposed laterally adjacent to and insulated from the floating gate.

    Abstract translation: 非易失性存储单元包括第一导电类型的衬底，具有第二导电类型的第一区域，与第一区域间隔开的第二导电类型的第二区域，在它们之间形成沟道区域。 浮置栅极设置在与第一区域相邻的沟道区域的第一部分之上并与其绝缘。 选择栅极设置在与第二区域相邻的沟道区域的第二部分上，选择栅极由金属材料形成并且通​​过二氧化硅层和高层与沟道区域的第二部分绝缘 K绝缘材料。 控制栅极设置在浮动栅极上并与浮动栅极绝缘。 擦除栅极设置在第一区域的上方并与第一区域绝缘，并且横向地邻近浮动栅极并与其隔离。

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