公开(公告)号：US06936506B1

公开(公告)日：2005-08-30

申请号：US10442975

申请日：2003-05-22

Applicant: James F. Buller ,  Derick J. Wristers ,  Qi Xiang ,  Bin Yu

Inventor： James F. Buller ,  Derick J. Wristers ,  Qi Xiang ,  Bin Yu

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/10

CPC classification number: H01L21/823807 ,  H01L29/1054

Abstract: A method of manufacturing a semiconductor device includes providing a strained-silicon semiconductor layer over a silicon germanium layer, and partially removing a first portion of the strained-silicon layer. The strained-silicon layer includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the strained-silicon layer initially can have the same thickness. A p-channel transistor is formed over the first portion, and a n-channel transistor is formed over the second portion. A semiconductor device is also disclosed.

Abstract translation: 制造半导体器件的方法包括在硅锗层上提供应变硅半导体层，并部分去除应变硅层的第一部分。 应变硅层包括第一部分和第二部分，第二部分的厚度大于第一部分的厚度。 最初，应变硅层的第一和第二部分最初可以具有相同的厚度。 在第一部分上形成p沟道晶体管，并且在第二部分上形成n沟道晶体管。 还公开了一种半导体器件。

公开(公告)号：US06924561B1

公开(公告)日：2005-08-02

申请号：US10728910

申请日：2003-12-08

Applicant: Wiley Eugene Hill ,  Bin Yu

Inventor： Wiley Eugene Hill ,  Bin Yu

IPC: H01L21/336 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1108 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1211 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903 ,  Y10S438/944

Abstract: A memory device includes multiple fins formed adjacent to one another, a source region, a drain region, a gate, a wordline, and a bitline contact. At least one of the multiple fins is doped with a first type of impurities and at least one other one of the fins is doped with a second type of impurities. The source region is formed at one end of each of the fins and the drain region is formed at an opposite end of each of the fins. The gate is formed over two of the multiple fins, the wordline is formed over each of the multiple fins, and a bitline contact is formed adjacent at least one of the multiple fins.

Abstract translation: 存储器件包括彼此相邻形成的多个鳍，源极区，漏极区，栅极，字线和位线接触。 多个翅片中的至少一个被掺杂有第一类型的杂质，并且至少另外一个翅片掺杂有第二类型的杂质。 源区域形成在每个散热片的一端，并且漏极区域形成在每个散热片的相对端。 栅极形成在多个散热片的两个之上，字线形成在多个散热片的每一个上，并且与多个散热片中的至少一个相邻地形成有位线接触。

公开(公告)号：US06902966B2

公开(公告)日：2005-06-07

申请号：US09983625

申请日：2001-10-25

Applicant: Bin Yu ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Qi Xiang

Inventor： Bin Yu ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Qi Xiang

IPC: H01L21/28 ,  H01L21/20 ,  H01L21/265 ,  H01L21/268 ,  H01L21/336 ,  H01L29/417 ,  H01L29/78 ,  H01L21/00

CPC classification number: H01L29/665 ,  H01L21/268

Abstract: A method of manufacturing a MOSFET semiconductor device comprises forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate; forming source/drain extensions in the substrate; forming first and second sidewall spacers; implanting dopants within the substrate to form source/drain regions in the substrate adjacent to the sidewalls spacers; laser thermal annealing to activate the source/drain regions; depositing a layer of nickel over the source/drain regions; and annealing to form a nickel silicide layer disposed on the source/drain regions. The source/drain extensions and sidewall spacers are adjacent to the gate electrode. The source/drain extensions can have a depth of about 50 to 300 angstroms, and the source/drain regions can have a depth of about 400 to 1000 angstroms. The annealing is at temperatures from about 350 to 500° C.

Abstract translation: 一种制造MOSFET半导体器件的方法包括：在栅极电极和衬底之间形成衬底上的栅电极和栅极氧化物; 在衬底中形成源极/漏极延伸部; 形成第一和第二侧壁间隔物; 在所述衬底内注入掺杂剂以在所述衬底中邻近所述侧壁间隔物形成源/漏区; 激光热退火激活源/漏区; 在源极/漏极区域上沉积镍层; 并退火以形成设置在源/漏区上的硅化镍层。 源极/漏极延伸部和侧壁间隔物与栅电极相邻。 源极/漏极延伸部可以具有约50至300埃的深度，并且源极/漏极区域可以具有约400至1000埃的深度。 退火温度在约350-500℃

公开(公告)号：US20050118824A1

公开(公告)日：2005-06-02

申请号：US11030191

申请日：2005-01-07

Applicant: Krishnashree Achuthan ,  Shibly Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Krishnashree Achuthan ,  Shibly Ahmed ,  Haihong Wang ,  Bin Yu

IPC: C09G1/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/00 ,  H01L21/302 ,  H01L21/3205 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/84

CPC classification number: H01L29/785 ,  C09G1/02 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/6681 ,  Y10S438/959

Abstract: A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial “rough” planarization and then a “fine” planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.

Abstract translation: 制造MOSFET型半导体器件的方法包括平坦化沉积在沟道上的栅极材料层。 平面化在包括初始“粗糙”平坦化然后是“精细”平坦化的多步骤过程中进行。 用于更精细平坦化的浆料可以包括倾向于粘附到栅极材料的低区域的添加材料。

公开(公告)号：US06867101B1

公开(公告)日：2005-03-15

申请号：US09826472

申请日：2001-04-04

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21/28 ,  H01L21/314 ,  H01L21/318 ,  H01L29/49 ,  H01L29/51 ,  H01L21/336 ,  H01L21/31 ,  H01L21/3205

CPC classification number: H01L21/28194 ,  H01L21/28202 ,  H01L21/3141 ,  H01L21/3144 ,  H01L21/3185 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A method of fabricating a semiconductor device, having a nitride/high-k material/nitride gate dielectric stack with good thermal stability which does not diffuse into a silicon substrate, a polysilicon gate, or a polysilicon-germanium gate when experiencing subsequent high temperature processes, involving: (a) providing a substrate; (b) initiating formation of the nitride/high-k material/nitride gate dielectric stack by depositing a first ultra-thin nitride film on the substrate; (c) depositing a high-k material, such as a thin metal film, on the first ultra-thin nitride film; (d) depositing a second ultra-thin nitride film on the high-k material, thereby forming a sandwich structure; (e) completing formation of the nitride/high-k material/nitride gate dielectric stack from the sandwich structure; and (f) completing fabrication of the semiconductor device.

Abstract translation: 一种制造半导体器件的方法，其具有具有良好热稳定性的氮化物/高k材料/氮化物栅极电介质叠层，当经历随后的高温处理时，其不扩散到硅衬底，多晶硅栅极或多晶硅锗栅极 涉及：（a）提供底物; （b）通过在衬底上沉积第一超薄氮化物膜来引发氮化物/高k材料/氮化物栅极电介质叠层的形成; （c）在第一超薄氮化物膜上沉积诸如金属薄膜的高k材料; （d）在高k材料上沉积第二超薄氮化物膜，由此形成夹层结构; （e）从夹层结构完成氮化物/高k材料/氮化物栅极电介质堆叠的形成; 和（f）完成半导体器件的制造。

公开(公告)号：US06867080B1

公开(公告)日：2005-03-15

申请号：US10460165

申请日：2003-06-13

Applicant: Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

Inventor： Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

IPC: H01L21/20 ,  H01L21/268 ,  H01L21/28 ,  H01L21/321 ,  H01L21/8234 ,  H01L21/338 ,  H01L21/331 ,  H01L21/94

CPC classification number: H01L21/28176 ,  H01L21/2026 ,  H01L21/268 ,  H01L21/28035 ,  H01L21/321 ,  H01L21/823437 ,  Y10S438/926

Abstract: A method is provided for eliminating uneven heating of substrate active areas during laser thermal annealing (LTA) due to variations in gate electrode density. Embodiments include adding dummy structures, formed simultaneously with the gate electrodes, to “fill in” the spaces between isolated gate electrodes, such that the spacing between the gate electrodes and the dummy structures is the same as the spacing between the densest array of device structures on the substrate surface. Since the surface features (i.e., the gate electrodes and the dummy structures) appear substantially uniform to the LTA laser, the laser radiation is uniformly absorbed by the substrate, and the substrate surface is evenly heated.

Abstract translation: 提供了一种用于消除激光热退火（LTA）期间基板有源区的不均匀加热的方法，这是由于栅电极密度的变化。 实施例包括添加与栅电极同时形成的虚拟结构以“填充”隔离栅电极之间的空间，使得栅电极和虚拟结构之间的间隔与器件结构最密集阵列之间的间隔相同 在基板表面上。 由于表面特征（即，栅电极和虚拟结构）对于LTA激光器而言基本上均匀，激光辐射被基板均匀地吸收，并且基板表面被均匀地加热。

公开(公告)号：US20050006666A1

公开(公告)日：2005-01-13

申请号：US10913409

申请日：2004-08-09

Applicant: Bin Yu ,  Shibly Ahmed ,  Judy An ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic ,  Haihong Wang

Inventor： Bin Yu ,  Shibly Ahmed ,  Judy An ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic ,  Haihong Wang

IPC: H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L31/072

CPC classification number: H01L29/785 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/66803

Abstract: A method of forming a semiconductor device includes forming a fin on an insulating layer, where the fin includes a number of side surfaces, a top surface and a bottom surface. The method also includes forming a gate on the insulating layer, where the gate has a substantially U-shaped cross-section at a channel region of the semiconductor device.

Abstract translation: 形成半导体器件的方法包括在绝缘层上形成翅片，其中鳍片包括多个侧表面，顶表面和底表面。 该方法还包括在绝缘层上形成栅极，其中栅极在半导体器件的沟道区域具有基本上U形的横截面。

公开(公告)号：US06827840B2

公开(公告)日：2004-12-07

申请号：US10170903

申请日：2002-06-13

Applicant: Kalle Levon ,  Bin Yu ,  Yanxiu Zhou

Inventor： Kalle Levon ,  Bin Yu ,  Yanxiu Zhou

IPC: G01N27327

CPC classification number: G01N27/3335

Abstract: Enantiomeric resolution is realized by combining an electrochemical method with ligand exchange (LE) in a novel electrochemical method named chiral ligand exchange potentiometry. Chiral selector ligands preferentially recognize certain enantiomers and undergo ligand exchange with the enantiomeric labile coordination complexes to form diastereoisomeric complexes. These complexes can form in solution and be recognized by an unmodified electrode, or they can be immobilized on the surface of a modified electrode (chiral sensor) incorporated with the chiral selector ligand by polysiloxane monolayer immobilization (PMI). Considerable stereoselectivity occurs in the formation of these diastereoisomeric complexes, and their net charges (Nernst factors) are different, thus enabling enantiomers to be distinguished by potentiometric electrodes without any pre-separation processes.

Abstract translation: 通过将电化学方法与配体交换（LE）结合在一种称为手性配体交换电位法的新型电化学方法中来实现对映体拆分。 手性选择配体优先识别某些对映异构体并与对映异构体不稳定配位络合物进行配体交换以形成非对映异构体复合物。 这些配合物可以在溶液中形成并被未改性的电极识别，或者它们可以通过聚硅氧烷单层固定化（PMI）固定在掺入手性选择配体的改性电极（手性传感器）的表面上。 在形成这些非对映异构体复合物时会产生相当大的立体选择性，它们的净电荷（能斯特因子）是不同的，因此能够通过电位电极区分对映异构体，而无需任何预分离过程。

公开(公告)号：US06825115B1

公开(公告)日：2004-11-30

申请号：US10341436

申请日：2003-01-14

Applicant: Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

Inventor： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

IPC: H01L2144

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/28518 ,  H01L29/665

Abstract: Dopant deactivation, particularly at the Si/silicide interface, is avoided by forming deep source/drain implants after forming silicide layers on the substrate and activating the source/drain regions by laser thermal annealing. Embodiments include forming source/drain extensions, forming metal silicide layers on the substrate surface and gate electrode, forming preamorphized regions under the metal silicide layers in the substrate, ion implanting to form deep source/drain implants overlapping the preamorphized regions and extending deeper into the substrate then the preamorphized regions, and laser thermal annealing to activate the deep source/drain regions.

Abstract translation: 通过在衬底上形成硅化物层并通过激光热退火来激活源极/漏极区域之后形成深源极/漏极注入来避免掺杂失活，特别是Si /硅化物界面。 实施例包括形成源极/漏极延伸部，在衬底表面上形成金属硅化物层和栅电极，在衬底中的金属硅化物层下方形成预变形区域;离子注入，以形成与预变形区域重叠的深源/漏植入物， 衬底然后是前变形区域，激光热退火激活深源/漏区。

公开(公告)号：USRE38608E1

公开(公告)日：2004-10-05

申请号：US10052843

申请日：2002-01-17

Applicant: Bin Yu ,  Chenming Hu ,  Ya-Chin King ,  Jeffrey T. Pohlman ,  Rita Trivedi

Inventor： Bin Yu ,  Chenming Hu ,  Ya-Chin King ,  Jeffrey T. Pohlman ,  Rita Trivedi

IPC: H01L2900

CPC classification number: H01L29/8618 ,  H01L29/866

Abstract: A punch-through diode transient suppression device has a base region of varying doping concentration to improve leakage and clamping characteristics. The punch-through diode includes a first region comprising an n+ region, a second region comprising a p− region abutting the first region, a third region comprising a p+ region abutting the second region, and a fourth region comprising an n+ region abutting the third region. The peak dopant concentration of the n+ layers should be about 1.5E18 cm−3, the peak dopant concentration of the p+ layer should be between about 1 to about 5 times the peak concentration of the n+ layer, and the dopant concentration of the p− layer should be between about 0.5E14 cm−3 and about 1.OE17 cm−3. The junction depth of the fourth (n+) region should be greater than about 0.3 &mgr;m. The thickness of the third (p+) region should be between about 0.3 &mgr;m and about 2.0 &mgr;m, and the thickness of the second (p−) region should be between about 0.5 &mgr;m and about 5.0 &mgr;m.