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    COFDM demodulator with an optimal FFT analysis window positioning
    341.
    发明申请
    COFDM demodulator with an optimal FFT analysis window positioning 有权
    COFDM解调器具有最佳的FFT分析窗口定位

    公开(公告)号：US20030138060A1

    公开(公告)日：2003-07-24

    申请号：US10349561

    申请日：2003-01-22

    Applicant: STMicroelectronics S.A.

    Inventor： Nicole Alcouffe

    IPC: H04L027/14

    CPC classification number: H04L25/0232 ,  H04L5/0048 ,  H04L25/022 ,  H04L27/2662 ,  H04L27/2665

    Abstract: A COFDM demodulator or analogue comprising a fast Fourier transform circuit analyzing a received signal in a window corresponding to a symbol, each symbol conveying several phase- and/or amplitude-modulated carriers, some of which are signaling carriers, and a circuit for positioning said window. The circuit for positioning said window uses the non demodulated signaling carriers.

    Abstract translation: 一种COFDM解调器或模拟装置，其包括快速傅立叶变换电路，其分析与符号对应的窗口中的接收信号，每个符号传送数个相位和/或幅度调制的载波，其中一些是信令载波，以及用于定位所述 窗口。 用于定位所述窗口的电路使用未解调的信令载波。

    Isolating trench and manufacturing process
    342.
    发明申请
    Isolating trench and manufacturing process 有权
    隔离沟槽和制造工艺

    公开(公告)号：US20030098493A1

    公开(公告)日：2003-05-29

    申请号：US10272444

    申请日：2002-10-16

    Applicant: STMicroelectronics S.A.

    Inventor： Michel Marty ,  Francois Leverd ,  Philippe Coronel ,  Joaquin Torres

    IPC: H01L021/8238 ,  H01L029/00

    CPC classification number: H01L21/76229 ,  H01L21/764

    Abstract: An isolation trench formed in a semiconductor substrate has side walls and a bottom wall. Spacers are on the side walls and face each other for forming a narrow channel therebetween. The bottom wall and the spacers are coated with an electrically insulating material for delimiting a closed empty cavity in the channel. The isolation trench is applicable to the manufacture of integrated circuits.

    Abstract translation: 在半导体衬底中形成的隔离沟具有侧壁和底壁。 隔板在侧壁上并且彼此面对以在它们之间形成狭窄的通道。 底壁和间隔物涂覆有用于限定通道中的封闭空腔的电绝缘材料。 隔离沟槽适用于集成电路的制造。

    Method and circuit of digital measurement of the phase of a sinusoidal signal
    343.
    发明申请
    Method and circuit of digital measurement of the phase of a sinusoidal signal 有权

    公开(公告)号：US20030072361A1

    公开(公告)日：2003-04-17

    申请号：US10273016

    申请日：2002-10-16

    Applicant: STMicroelectronics S.A.

    Inventor： Patrick Simeoni

    IPC: H04Q001/20 ,  H04B003/46

    CPC classification number: G11B7/0901 ,  H04L7/0334 ,  H04L2007/047

    Abstract: A method for measuring with a maximum error E the phase of a substantially sinusoidal signal, of angular frequency nullnull2null/T, sampled with a sampling period T/r, in which the phase is calculated as the time at which a straight line crossing two consecutive samples located on either side of a median value of the signal reaches said value, including the step of selecting number r from a range included between a value r0 and a value equal to from two to three times value r0, such that: 1 E null max t null [ - T r0 , 0 ] null [ t - T r0 null round null ( G null sin null null null null null null null t ) round null ( sin null [ G null null null t + 2 null null r0 ] ) - round null ( G null sin null null null null null null null t ) ] round(x) being the integer closest to a real number x and G being equal to 2iG1, where i is the number of bits on which are coded the samples and where G1 is a term of correction of the amplitude of the sampled signal.

    Digital sample sequence conversion device
    344.
    发明申请
    Digital sample sequence conversion device 有权
    数字采样序列转换装置

    公开(公告)号：US20030065463A1

    公开(公告)日：2003-04-03

    申请号：US10184017

    申请日：2002-06-26

    Applicant: STMicroelectronics S.A.

    Inventor： Thierry Lenez ,  Eric Petit

    IPC: G06F019/00

    CPC classification number: H03H17/0275 ,  H03H17/0685

    Abstract: A device for automatically converting a digital sample sequence X(n) inputted at a first frequency fe and converted into an output digital sample sequence Y(m) at a second frequency fs which is smaller than fe. An interpolator-decimator assembly having a decimation rate equal to null, selected so as to correspond to the frequency offset fe/fs is based on a polyphased filter having p tables of q elements each, said filter being designed such that samples X(n) are input at the fe frequency and table components are activated according to clocking of a second clock derived from the fe clock and wherein one clock pulse is removed.

    Abstract translation: 一种用于自动转换以第一频率fe输入的数字采样序列X（n）并以小于fe的第二频率fs转换成输出数字采样序列Y（m）的装置。 具有等于​​γ的抽取率等于γ的内插器 - 抽取器组件基于具有每个q个元件的p个表的多相滤波器，所述滤波器被设计为使得样本X（n） 以fe频率输入，并且根据从时钟导出的第二时钟的时钟激活表分量，并且其中一个时钟脉冲被去除。

    Lateral operation bipolar transistor and a corresponding fabrication process
    346.
    发明申请
    Lateral operation bipolar transistor and a corresponding fabrication process 有权
    横向操作双极晶体管和相应的制造工艺

    公开(公告)号：US20030025125A1

    公开(公告)日：2003-02-06

    申请号：US10142249

    申请日：2002-05-09

    Applicant: STMICROELECTRONICS S.A.

    Inventor： Olivier Menut ,  Herve Jaouen

    IPC: H01L029/74

    CPC classification number: H01L29/1012 ,  H01L29/0649 ,  H01L29/735

    Abstract: The transistor includes an emitter region 17 disposed in a first isolating well 11, 150 formed in a semiconductor bulk. An extrinsic collector region 16 is disposed in a second isolating well 3, 150 formed in the semiconductor bulk SB and separated laterally from the first well by a bulk separator area 20. An intrinsic collector region is situated in the bulk separator area 20 in contact with the extrinsic collector region. An intrinsic base region 100 is formed which is thinner laterally than vertically and in contact with the intrinsic collector region and in contact with the emitter region through bearing on a vertical flank of the first isolating well facing a vertical flank of the second isolating well. An extrinsic base region 60 is formed which is substantially perpendicular to the intrinsic base region in the top part of the bulk separator area, and contact terminals C, B, E respectively in contact with the extrinsic collector region, the extrinsic base region, and the emitter region.

    Abstract translation: 晶体管包括设置在半导体本体中形成的第一隔离阱11,150中的发射极区17。 非本征集电极区域16设置在形成于半导体本体SB中的第二隔离阱3,150中，并通过体分离器区域20与第一阱的横向分离。本体集电极区域位于与本体分离器区域20接触的本体分离器区域20中 外部集电极区域。 形成本征基区100，其横向比垂直地更薄并且与本征收集区相接触，并且通过轴承在第一隔离井的垂直侧面与第二隔离井的垂直侧面的垂直侧面接触。 形成基本上垂直于本体分离器区域的顶部中的本征基极区域的外部基极区域60，以及分别与外部基极区域，外部基极区域和外部基极区域接触的接触端子C，B，E 发射区。

    DRAM cell refreshment method and circuit
    347.
    发明申请
    DRAM cell refreshment method and circuit 有权
    DRAM单元刷新方法和电路

    公开(公告)号：US20030022427A1

    公开(公告)日：2003-01-30

    申请号：US10186289

    申请日：2002-06-27

    Applicant: STMicroelectronics S.A.

    Inventor： Richard Ferrant ,  Florent Vautrin

    IPC: H01L021/8238

    CPC classification number: G11C11/406

    Abstract: A device and a method for refreshing the voltage of a circuit line that provides the capability of bringing the circuit line to a ground voltage or to a first voltage. The method provides storing the circuit line voltage in a capacitor; and controlling, by means of the stored voltage, a switch connecting the circuit line to a second voltage of absolute value greater than the first voltage, whereby the circuit line is set to the second voltage if, during the step of storing, the circuit line was at the first voltage.

    Abstract translation: 一种用于刷新电路线路的电压的装置和方法，其提供使电路线路接地电压或第一电压的能力。 该方法提供将电路线电压存储在电容器中; 以及通过所存储的电压来控制将所述电路线连接到绝对值大于所述第一电压的第二电压的开关，由此在所述电路线路的存储步骤期间将所述电路线设置为所述第二电压 处于第一电压。

    Method of fabricating an integrated circuit and an integrated circuit with a monocrystalline silicon substrate
    348.
    发明申请
    Method of fabricating an integrated circuit and an integrated circuit with a monocrystalline silicon substrate 有权
    制造集成电路的方法和具有单晶硅衬底的集成电路

    公开(公告)号：US20030013262A1

    公开(公告)日：2003-01-16

    申请号：US10171102

    申请日：2002-06-13

    Applicant: STMICROELECTRONICS S.A.

    Inventor： Olivier Menut ,  Herve Jaouen

    IPC: H01L021/331 ,  H01L021/22 ,  H01L021/38

    CPC classification number: H01L29/66272

    Abstract: A method of fabricating an integrated circuit including a monocrystalline silicon substrate, a layer of polycrystalline silicon on the top surface of the substrate and doped with at least two dopants with different rates of diffusion, in which method annealing is performed at a temperature and for a time such that a first dopant diffuses into a first zone and a second dopant diffuses into a second zone larger than the first zone.

    Abstract translation: 一种制造集成电路的方法，该集成电路包括单晶硅衬底，在该衬底的顶表面上的多晶硅层，并且掺杂有至少两种具有不同扩散速率的掺杂剂，其中在温度和 时间，使得第一掺杂剂扩散到第一区域中，并且第二掺杂剂扩散到大于第一区域的第二区域中。

    Dram cell reading method and device
    350.
    发明申请
    Dram cell reading method and device 有权
    戏剧细胞阅读方法和装置

    公开(公告)号：US20020159321A1

    公开(公告)日：2002-10-31

    申请号：US10135981

    申请日：2002-04-29

    Applicant: STMicroelectronics S.A.

    Inventor： Francois Jacquet ,  Florent Vautrin

    IPC: G11C007/00

    CPC classification number: G11C7/062 ,  G11C7/14 ,  G11C11/406 ,  G11C11/4091

    Abstract: A device for reading from a capacitive memory cell, including a comparator of the voltage stored in the memory cell with respect to a reference value, which exhibits a high input impedance; a refreshment means distinct from the comparator, the refreshment means having a low output impedance and being controlled by the comparator to impose a refreshment voltage to the memory cell; and means for controllably connecting the refreshment means to the memory cell.

    Abstract translation: 一种用于从电容存储单元读取的装置，包括相对于参考值存储在存储单元中的电压的比较器，该比较器具有高输入阻抗; 与比较器不同的刷新装置，刷新装置具有低输出阻抗并由比较器控制以向存储器单元施加刷新电压; 以及用于将所述刷新装置可控地连接到所述存储单元的装置。

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