公开(公告)号：US20240363373A1

公开(公告)日：2024-10-31

申请号：US18770574

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chun HSU ,  Shu-Yen WANG ,  Chui-Ya PENG

IPC: H01L21/67 ,  H01L21/02

CPC classification number: H01L21/67057 ,  H01L21/02057 ,  H01L21/67034 ,  H01L21/67248 ,  H01L21/67253

Abstract: A system and method includes: immersing a wafer in a bath within a cleaning chamber, removing the wafer out of the bath through a solvent and into a gas within the cleaning chamber, determining a parameter value from the gas; and performing remediation within the cleaning chamber in response to determining that the parameter value is beyond a threshold value.

公开(公告)号：US20240363359A1

公开(公告)日：2024-10-31

申请号：US18308266

申请日：2023-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Tsu Chung ,  Yung-Chi Lin ,  Yen-Ming Chen

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/3213

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/32137

Abstract: A method includes forming a patterned treating mask over a first surface dielectric layer of a first package component, wherein portions of the first surface dielectric layer are exposed through the patterned treating mask, performing a selective plasma treatment on the portions of the first surface dielectric layer that are exposed through the patterned treating mask to form treated portions, removing the patterned treating mask, and bonding a second surface dielectric layer in a second package component to the first surface dielectric layer.

公开(公告)号：US20240363353A1

公开(公告)日：2024-10-31

申请号：US18449443

申请日：2023-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pin-Wen Chen ,  Yu-Chen Ko ,  Chi-Yuan Chen ,  Ya-Yi Cheng ,  Chun-I Tsai ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai ,  Syun-Ming Jang ,  Wei-Jen Lo

IPC: H01L21/285 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/28518 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming a source/drain region over the fin adjacent to the gate structure; forming an interlayer dielectric (ILD) layer over the source/drain region around the gate structure; forming an opening in the ILD layer to expose the source/drain region; forming a silicide region and a barrier layer successively in the openings over the source/drain region, where the barrier layer includes silicon nitride; reducing a concentration of silicon nitride in a surface portion of the barrier layer exposed to the opening; after the reducing, forming a seed layer on the barrier layer; and forming an electrically conductive material on the seed layer to fill the opening.

公开(公告)号：US20240363351A1

公开(公告)日：2024-10-31

申请号：US18765720

申请日：2024-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3115 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/28088 ,  H01L21/0259 ,  H01L21/28185 ,  H01L21/28518 ,  H01L21/3115 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/0673

Abstract: In some embodiments, a method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form first recesses; forming source/drain regions in the first recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; performing an aluminum treatment on the gate dielectric; depositing a first conductive material over and around the gate dielectric; performing a fluorine treatment on the first conductive material; and depositing a second conductive material over and around the first conductive material.

公开(公告)号：US20240363339A1

公开(公告)日：2024-10-31

申请号：US18771110

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Min-Hsiu Hung ,  Hung-Yi Huang ,  Chun Chieh Wang ,  Yu-Ting Lin

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/532

CPC classification number: H01L21/02274 ,  H01L21/28518 ,  H01L21/762 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76889 ,  H01L21/823864 ,  H01L23/53266 ,  H01L21/823418

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

公开(公告)号：US20240363336A1

公开(公告)日：2024-10-31

申请号：US18771426

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Joung-Wei Liou ,  Yu Lun Ke ,  Yi-Wei Chiu

IPC: H01L21/02 ,  H01L21/768

CPC classification number: H01L21/02164 ,  H01L21/02205 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/76802 ,  H01L21/76877

Abstract: Methods to form low-k dielectric materials for use as intermetal dielectrics in multilevel interconnect systems, along with their chemical and physical properties, are provided. The deposition techniques described include PECVD, PEALD, and ALD processes where the precursors such as TEOS and MDEOS may provide the requisite O-atoms and O2 gas may not be used as one of the reactants. The deposition techniques described further include PECVD, PEALD, and ALD processes where O2 gas may be used and, along with the O2 gas, precursors containing embedded Si—O—Si bonds, such as (CH3O)3—Si—O—Si—(CH3O)3) and (CH3)3—Si—O—Si—(CH3)3 may be used.

公开(公告)号：US20240361203A1

公开(公告)日：2024-10-31

申请号：US18770570

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei Cheng CHIU

IPC: G01M3/28 ,  G01M3/02 ,  G01M13/00 ,  G01M13/003 ,  G01M13/005 ,  H01L21/67

CPC classification number: G01M3/2876 ,  G01M3/02 ,  G01M13/00 ,  G01M13/003 ,  G01M13/005 ,  H01L21/67017

Abstract: A system and method for cleaning and inspecting ring frames is disclosed here. In one embodiment, a vacuum valve comprising at least one sealing O-ring; and a pressure monitoring tape on a mating surface on a vacuum processing chamber, wherein the pressure monitoring tape is configured to perform a pressure profile mapping between the mating surface on the vacuum processing chamber and a surface of the at least one sealing O-ring on the vacuum valve to determine a closing condition of the vacuum valve.

公开(公告)号：US12133467B2

公开(公告)日：2024-10-29

申请号：US17876393

申请日：2022-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ting-Jung Chen

IPC: H10N30/063 ,  H10N30/09 ,  H10N30/50 ,  H10N30/87

CPC classification number: H10N30/063 ,  H10N30/09 ,  H10N30/50 ,  H10N30/872

Abstract: A method for forming a MEMS device is provided. The method includes forming a stack of layers on a base piezoelectric layer. The stack of layers includes a base metal film over the base piezoelectric layer; a first piezoelectric film over the base metal film; and a first metal film having an opening therein over the first piezoelectric film. The method also includes forming a trench in the stack of layers, wherein the trench passes through the opening in the first metal film but does not expose the base metal film; after forming the trench, forming a spacer structure under the first metal film but spaced apart from the base metal film; after forming the spacer structure, deepening the trench to expose the base metal film; and forming a contact in the trench.

公开(公告)号：US12132118B2

公开(公告)日：2024-10-29

申请号：US17231183

申请日：2021-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Min Liu ,  Li-Li Su ,  Yee-Chia Yeo

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/0665 ,  H01L29/66742

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin as an initial step in forming a source/drain region. The opening is formed into a parasitic channel region of the fin. Once the opening has been formed, a first semiconductor material is epitaxially grown at the bottom of the opening to a level over the top of the parasitic channel region. A second semiconductor material is epitaxially grown from the top of the first semiconductor material to fill and/or overfill the opening. The second semiconductor material is differently doped from the first semiconductor material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the nanostructures.

公开(公告)号：US12132091B2

公开(公告)日：2024-10-29

申请号：US17532062

申请日：2021-11-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang Cheng ,  Ziwei Fang ,  Chun-I Wu ,  Huang-Lin Chao

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42372 ,  H01L21/823431 ,  H01L21/823443 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: The embodiments described herein are directed to a method for the fabrication of transistors with aluminum-free n-type work function layers as opposed to aluminum-based n-type work function layers. The method includes forming a channel portion disposed between spaced apart source/drain epitaxial layers and forming a gate stack on the channel portion, where forming the gate stack includes depositing a high-k dielectric layer on the channel portion and depositing a p-type work function layer on the dielectric layer. After depositing the p-type work function layer, forming without a vacuum break, an aluminum-free n-type work function layer on the p-type work function layer and depositing a metal on the aluminum-free n-type work function layer. The method further includes depositing an insulating layer to surround the spaced apart source/drain epitaxial layers and the gate stack.