公开(公告)号：US6049096A

公开(公告)日：2000-04-11

申请号：US61666

申请日：1998-04-16

Applicant: Eric Bernier

Inventor： Eric Bernier

IPC: H01L29/74 ,  H01L27/02 ,  H01L29/747 ,  H01L31/111

CPC classification number: H01L27/0248

Abstract: The present invention relates to a component protecting against electric overloads likely to occur on a conductor in series with which is placed a detection resistor. The component includes a first cathode-gate thyristor and a second anode-gate thyristor, of the gate current or forward break-over type. The anode region of the first thyristor, formed on the lower surface side, is separate from the isolating wall surrounding the thyristor and the rear surface of the isolating wall is coated with a portion of an insulating layer.

Abstract translation: 本发明涉及一种防止可能发生在串联的导体上的电过载的部件，其中放置有检测电阻器。 该组件包括栅极电流或正向断开型的第一阴极栅极晶闸管和第二阳极栅极晶闸管。 形成在下表面侧的第一晶闸管的阳极区域与围绕晶闸管的隔离壁分离，并且隔离壁的后表面涂覆有绝缘层的一部分。

公开(公告)号：US5973515A

公开(公告)日：1999-10-26

申请号：US097286

申请日：1998-06-12

Applicant: Roland Marbot ,  Pascal Couteaux ,  Anne Pierre Duplessix ,  Reza Nezamzadeh ,  Jean-Claude Le Bihan ,  Michel D'Hoe ,  Francis Mottini

Inventor： Roland Marbot ,  Pascal Couteaux ,  Anne Pierre Duplessix ,  Reza Nezamzadeh ,  Jean-Claude Le Bihan ,  Michel D'Hoe ,  Francis Mottini

IPC: H03F3/45 ,  H03K19/0185 ,  H04L25/02 ,  H03K5/22

CPC classification number: H04L25/0292 ,  H03F3/45475 ,  H03F3/45928 ,  H03K19/018528 ,  H04L25/0274 ,  H04L25/0286

Abstract: An integrated circuit comprises at least one differential input stage. The differential input stage includes an input circuit and a shaping circuit. The input circuit comprises a first portion and a second portion for providing two pairs of differential signals. The propagation times of the first and second circuit portions are preferably substantially identical. The shaping circuit differentiates each of the two pairs of differential signals and combines them to obtain a single binary type of signal.

Abstract translation: 集成电路包括至少一个差分输入级。 差分输入级包括输入电路和整形电路。 输入电路包括用于提供两对差分信号的第一部分和第二部分。 优选地，第一和第二电路部分的传播时间基本相同。 整形电路区分两对差分信号中的每一对，并将它们组合以获得单个二进制类型的信号。

公开(公告)号：US5966110A

公开(公告)日：1999-10-12

申请号：US758207

申请日：1996-11-26

Applicant: Klaas Van Zalinge

Inventor： Klaas Van Zalinge

IPC: G09G3/14 ,  H05B33/08 ,  G09G3/32

CPC classification number: H05B33/0803 ,  G09G3/14 ,  H05B33/0818

Abstract: An LED driver drives a plurality of light emitting diodes (LEDs) having first terminals connected to a common output stage and second terminals respectively receiving different, suitably rectified, phases of a sinusoidal signal. An output stage of the LED driver includes a first bipolar transistor coupled between a first supply terminal and the first terminals of the LED's. A first MOS transistor drives the base of the first bipolar transistor. The gate of the first MOS transistor is coupled to a first reference voltage. A second bipolar cascode transistor is connected in series with the first MOS transistor and biased by a second reference voltage such that the voltage across the first MOS transistor does not exceed a limit value.

Abstract translation: LED驱动器驱动具有连接到公共输出级的第一端子和分别接收正弦信号的不同的，适当整流的相位的第二端子的多个发光二极管（LED）。 LED驱动器的输出级包括耦合在第一电源端子和LED的第一端子之间的第一双极晶体管。 第一MOS晶体管驱动第一双极晶体管的基极。 第一MOS晶体管的栅极耦合到第一参考电压。 第二双极级共源共栅晶体管与第一MOS晶体管串联连接并被第二参考电压偏置，使得第一MOS晶体管两端的电压不超过极限值。

公开(公告)号：US5850452A

公开(公告)日：1998-12-15

申请号：US509363

申请日：1995-07-31

Applicant: Laurent Sourgen ,  Sylvie Wuidart

Inventor： Laurent Sourgen ,  Sylvie Wuidart

IPC: G06F21/22 ,  G06F1/00 ,  G06F7/76 ,  G06F21/00 ,  G09C1/00 ,  H01L27/10 ,  H04L9/00

CPC classification number: G06F7/76 ,  G06F21/62 ,  G06F21/72 ,  G06F21/75

Abstract: The present invention concerns a method for the numerical scrambling by permutation of data bits in a programmable circuit comprising a control unit and at least one data bus (DBUS) to transmit data between the control unit and several memory circuits. It consists of having data on the bus either in a scrambled form or in an unscrambled form according to whether it is instructions data or not. And data in some of the memories is scrambled. The present invention also concerns a method for realising a permutation circuit.

Abstract translation: 本发明涉及一种用于通过在包括控制单元和至少一个数据总线（DBUS）的可编程电路中的数据位置换进行数字加扰的方法，以在控制单元和多个存储器电路之间传送数据。 它包括根据是否是指令数据，以加扰形式或未加扰形式在总线上进行数据。 并且一些存储器中的数据被加扰。 本发明还涉及一种用于实现置换电路的方法。

公开(公告)号：US09881965B2

公开(公告)日：2018-01-30

申请号：US12892372

申请日：2010-09-28

Applicant: Jérôme Vaillant

Inventor： Jérôme Vaillant

IPC: H01L31/0232 ,  H01L27/146

CPC classification number: H01L27/14645 ,  H01L27/1464

Abstract: A color back-side illuminated image sensor including, on the side of the thin semiconductor layer opposite to the illuminated surface, periodic thickness unevennesses forming an optic network having characteristics which make it capable of reflecting a given wavelength chosen within the range of the wavelengths of an illuminating incident beam.

公开(公告)号：US09704967B2

公开(公告)日：2017-07-11

申请号：US14853719

申请日：2015-09-14

Applicant: STMicroelectronics S.A.

Inventor： Pascal Chevalier ,  Didier Celi ,  Jean-Pierre Blanc ,  Alain Chantre

IPC: H01L29/66 ,  H01L21/82 ,  H01L29/737 ,  H01L21/8249 ,  H01L27/06

CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66325 ,  H01L29/737 ,  H01L29/7378

Abstract: The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches, and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess.

公开(公告)号：US09582675B2

公开(公告)日：2017-02-28

申请号：US14871873

申请日：2015-09-30

Applicant: STMICROELECTRONICS S.A.

Inventor： Albert Martinez ,  William Orlando

IPC: G06F21/62 ,  G06F12/14 ,  G06F21/52 ,  G06F21/79 ,  G06F21/60

CPC classification number: G06F21/62 ,  G06F12/1408 ,  G06F12/1483 ,  G06F21/52 ,  G06F21/602 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2221/033 ,  G06F2221/2105

Abstract: A method for loading a program, contained in at least a first memory, into a second memory accessible by an execution unit, in which the program is in a cyphered form in the first memory, a circuit for controlling the access to the second memory is configured from program initialization data, instructions of the program, and at least initialization data being decyphered to be transferred into the second memory after configuration of the circuit.

Abstract translation: 一种用于将包含在至少第一存储器中的程序加载到执行单元可访问的第二存储器中的方法，其中程序处于第一存储器中的加密形式，用于控制对第二存储器的访问的电路是 由程序初始化数据，程序的指令，以及至少初始化数据被解密以在电路配置之后被传送到第二存储器中。

公开(公告)号：US09224708B2

公开(公告)日：2015-12-29

申请号：US14339630

申请日：2014-07-24

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA

Inventor： Jean-Philippe Colonna ,  Perceval Coudrain

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L21/306 ,  H01L21/48 ,  H01L23/31 ,  H01L21/683

CPC classification number: H01L24/19 ,  H01L21/30604 ,  H01L21/4853 ,  H01L21/6836 ,  H01L21/7685 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/20 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13009 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13084 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13181 ,  H01L2224/13186 ,  H01L2224/1356 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13681 ,  H01L2224/13686 ,  H01L2224/14181 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention relates to a method for producing an interconnection pad on a conducting element comprising an upper face and a side wall; the method being executed from a substrate at least the upper face of which is insulating; the conducting element going through at least an insulating portion of the substrate, the method being characterized in that it comprises the sequence of the following steps: a step of embossing the conducting element, a step of forming, above the upper insulating face of the substrate, a stack of layers comprising at least one electrically conducting layer and one electrically resistive layer, a step of partially removing the electrically resistive layer, a step of electrolytic growth on the portion of the electrically conducting layer so as to form at least one interconnection pad on said conducting element.

Abstract translation: 本发明涉及一种用于在导电元件上制造互连焊盘的方法，包括上表面和侧壁; 所述方法从至少其上表面绝缘的衬底执行; 所述导电元件至少穿过所述基板的绝缘部分，所述方法的特征在于，其包括以下步骤的顺序：对所述导电元件进行压花的步骤，在所述基板的上绝缘面上方形成步骤 ，包括至少一个导电层和一个电阻层的层叠层，部分去除所述电阻层的步骤，在所述导电层的所述部分上的电解生长步骤，以便形成至少一个互连衬垫 在所述导电元件上。

公开(公告)号：US09077282B2

公开(公告)日：2015-07-07

申请号：US13745634

申请日：2013-01-18

Applicant: STMicroelectronics S.A. ,  International Business Machines Corporation

Inventor： Yvan Morandini ,  Romain Debrouke

IPC: H03B5/12 ,  H03B28/00 ,  H03H11/00 ,  H03J3/20

CPC classification number: H03B28/00 ,  H03B5/12 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1253 ,  H03B5/1265 ,  H03H11/00 ,  H03J3/20

Abstract: A variable capacitance device including: first and second transistors coupled in series by their main current nodes between first and second nodes of the device, a control node of the first transistor being adapted to receive a first control signal, and a control node of the second transistor being adapted to receive a second control signal; and control circuitry adapted to generate the first and second control signals from a selection signal.

Abstract translation: 一种可变电容器件，包括：第一和第二晶体管，其由器件的第一和第二节点之间的主要电流节点串联连接，第一晶体管的控制节点适于接收第一控制信号，第二晶体管的控制节点 晶体管适于接收第二控制信号; 以及适于从选择信号产生第一和第二控制信号的控制电路。

公开(公告)号：US09019666B2

公开(公告)日：2015-04-28

申请号：US13574497

申请日：2011-01-20

Applicant: Johan Bourgeat ,  Christophe Entringer ,  Philippe Galy ,  Jean Jimenez

Inventor： Johan Bourgeat ,  Christophe Entringer ,  Philippe Galy ,  Jean Jimenez

IPC: H02H9/00 ,  H02H9/04 ,  H01L23/60 ,  H01L27/02

CPC classification number: H02H9/044 ,  H01L23/60 ,  H01L27/0274 ,  H01L27/0277 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The electronic device includes a first (BP) and a second (BN) terminal and electronic means coupled between said two terminals; the electronic means include at least one block (BLC) comprising an MOS transistor (TR) including a parasitic bipolar transistor, the MOS transistor having the drain (D) thereof coupled to the first terminal (BP), the source (S) thereof coupled to the second terminal (BN) and being additionally configured, in the event of a current pulse (IMP) between the two terminals, to operate in a hybrid mode including MOS operation in a subthreshold mode and operation of the parasitic bipolar transistor. The device can comprise two blocks (BLC1, BLC2) connected symmetrically between the two terminals (BP, BN) with a triac (TRC) the trigger of which is connected to the common terminal (BC) of the two blocks.

Abstract translation: 电子设备包括耦合在所述两个终端之间的第一（BP）和第二（BN）终端和电子设备; 所述电子装置包括至少一个包括包括寄生双极晶体管的MOS晶体管（TR）的块（BLC），所述MOS晶体管的漏极（D）耦合到所述第一端子（BP），所述源极（S）耦合 （BN）并且在两个端子之间的电流脉冲（IMP）的情况下另外配置为以包括亚阈值模式中的MOS操作和寄生双极晶体管的操作的混合模式操作。 该装置可以包括两个端子（BP，BN）之间对称地连接有三端双向可控硅开关元件（TRC）的两个模块（BLC1，BLC2），触发器连接到两个模块的公共端子（BC）。