公开(公告)号：US10347619B2

公开(公告)日：2019-07-09

申请号：US15770624

申请日：2016-08-19

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Kui Xiao

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/866

Abstract: Disclosed is a semiconductor device having an electrostatic discharge protection structure. The electrostatic discharge protection structure is a diode connected between a gate electrode and a source electrode of the semiconductor device. The diode comprises a diode body and two connection portions connected to two ends of the diode body and respectively used for electrically connecting to the gate electrode and the source electrode. Lower parts of the two connection portions are respectively provided with a trench. An insulation layer is provided on an inner surface of the trench and the surface of a substrate between trenches. The diode body is provided on the insulation layer on the surface of the substrate. The connection portions respectively extend downwards into respective trenches from one end of the diode body. A dielectric layer is provided on the diode, and a metal conductor layer is provided on the dielectric layer.

公开(公告)号：US20190198665A1

公开(公告)日：2019-06-27

申请号：US16329663

申请日：2017-08-09

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Zheng BIAN

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/66734 ,  H01L29/78

Abstract: A VDMOS device and a manufacturing method therefor. The manufacturing method comprises: forming a groove in a semiconductor substrate, the groove comprising a first groove area, a second groove area, a third groove area, a fourth groove area and a fifth groove area; successively forming a first insulation layer, a first polycrystalline silicon layer and a second insulation layer on the semiconductor substrate; removing some of the second insulation layer until the first polycrystalline silicon layer is exposed; removing some of the first polycrystalline silicon layer, the remaining first polycrystalline silicon layer forming a first electrode; forming a third insulation layer on the semiconductor substrate, removing some of the third insulation layer, the second insulation layer and the first insulation layer, so that the top of the first polycrystalline silicon layer is higher than the top of the first insulation layer and the second insulation layer; and successively forming a gate oxide layer and a second polycrystalline silicon layer on the semiconductor substrate, and removing some of the second polycrystalline silicon layer, exposing the gate oxide layer located on the surface of the semiconductor substrate and the top of the second insulation layer, the remaining second polycrystalline silicon layer forming a second electrode.

公开(公告)号：US20190198644A1

公开(公告)日：2019-06-27

申请号：US16329656

申请日：2017-08-09

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Zheng BIAN

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/66734 ,  H01L21/28 ,  H01L29/423 ,  H01L29/4236 ,  H01L29/78 ,  H01L29/7813 ,  H01L29/7831

Abstract: A VDMOS device and a manufacturing method therefor. The method comprises: forming a groove in a semiconductor substrate, wherein the groove comprises a first groove area, a second groove area and a third groove area communicating with the first groove area and the second groove area, and the width of the first groove area is greater than the widths of the second groove area and the third groove area; forming an insulation layer on the semiconductor substrate; forming a first polycrystalline silicon layer on the insulation layer; removing some of the first polycrystalline silicon layer; the first polycrystalline silicon layer forming in the first groove being used as a first electrode of a deep gate; removing all the insulation layer located on the surface of the semiconductor substrate and some of the insulation layer located in the groove; forming a gate oxide layer on the semiconductor substrate; forming a second polycrystalline silicon layer on the gate oxide layer; removing some of the second polycrystalline silicon layer; and the second polycrystalline silicon layer forming in the groove being used as a second electrode of a shallow gate.

公开(公告)号：US20180375521A1

公开(公告)日：2018-12-27

申请号：US15741448

申请日：2016-05-10

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Xueyan WANG ,  Ying YANG ,  Jingjia YU

IPC: H03L7/081

CPC classification number: H03L7/0812 ,  H03L7/00 ,  H03L7/08

Abstract: A delay locked loop detection system (10), the system can be used for detecting the working state of a delay locked loop (400) and comprises: a signal generator (300), which is used for generating a reference clock and providing the reference clock to the delay locked loop (400); and a testing instrument (500), which is used for acquiring the clock signals output from the delay locked loop (400) and measuring whether the time delays thereof are consistent with expectations; the detection system (10) further comprises at least one of the following circuits: a pre-receiving circuit (100), which is used for receiving the reference clock from the signal generator (300) and amplifying and shaping the reference clock and then providing the reference clock to the delay locked loop (400); and a multiphase multiplexing circuit (200), which is used for receiving the clock signals output from the delay locked loop (400) and synthesizing and then providing a plurality of clock signals with different delay to the testing instrument (500). Also included is a delay locked loop detection method. The system and method mentioned above enable an accurate measurement for the delays of the delay locked loop.

公开(公告)号：US10093536B2

公开(公告)日：2018-10-09

申请号：US15573280

申请日：2016-05-10

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Errong Jing

IPC: G01J5/00 ,  B81C1/00 ,  B81B7/02 ,  G01J5/20

Abstract: An MEMS double-layer suspension microstructure manufacturing method, comprising: providing a substrate; forming a first dielectric layer on the substrate; patterning the first dielectric layer to prepare a first film body and a cantilever beam connected to the first film body; forming a sacrificial layer on the first dielectric layer; patterning the sacrificial layer located on the first film body to make a recess portioned portion for forming a support structure, with the first film body being exposed at the bottom of the recess portioned portion; forming a second dielectric layer on the sacrificial layer; patterning the second dielectric layer to make the second film body and the support structure, with the support structure being connected to the first film body and the second film body; and removing part of the substrate under the first film body and removing the sacrificial layer to obtain the MEMS double-layer suspension microstructure.

公开(公告)号：US20180262191A1

公开(公告)日：2018-09-13

申请号：US15748156

申请日：2016-05-12

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Chuan LUO

IPC: H03K17/687 ,  H03K17/10 ,  H03K19/0175

CPC classification number: H03K17/6871 ,  H03K17/102 ,  H03K17/687 ,  H03K17/6872 ,  H03K19/00 ,  H03K19/017545 ,  H03K2217/0054 ,  H03K2217/94

Abstract: A switch control circuit includes: a clock circuit (110) configured to generate a first clock control signal (CLK1) and a second clock control signal (CLK2); a voltage boosting circuit (120) configured to receive the second clock control signal (CLK2) and an operating voltage outputted by the power source (VDD); and boost the operating voltage by a preset value to form a switch control signal (H1) under the control of the second clock control signal (CLK2); and an inverting circuit (130) configured to receive the first clock control signal (CLK1) and the switch control signal (H1), and determine whether or not to output the switch control signal (H1) to the switch circuit according to the first clock control signal (CLK1), so as to control on/off of the switch circuit.

公开(公告)号：US10014392B2

公开(公告)日：2018-07-03

申请号：US15564172

申请日：2016-01-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun Qi ,  Guangsheng Zhang ,  Guipeng Sun ,  Sen Zhang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66681 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7823 ,  H01L29/7835

Abstract: Provided is a laterally diffused metal-oxide-semiconductor field-effect transistor, comprising a substrate (110), a source (150), a drain (140), a body region (160), a P-type field-limiting ring (135), and a well region on the substrate (110); the well region comprises an inserted well (122), which has P-type doping and is disposed below the drain and connected to the drain; N wells (124) disposed at the two sides of the inserted well (122); a P well (126) disposed next to the N well (124) and connected to the N well (124); a P-type field-limiting ring (135), which is disposed inside the N well (124), is a closed ring-shaped structure, and is located at the periphery below the drain (140); the inserted well (122) extends in its longitudinal direction to the position where it is in contact with said P-type field-limiting ring (135); the source (150) and the body region (160) are disposed inside the P well (126).

公开(公告)号：US20180139544A1

公开(公告)日：2018-05-17

申请号：US15573235

申请日：2016-05-05

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yonggang HU

IPC: H04R19/04 ,  H04R19/00 ,  H04R7/06 ,  H04R7/18 ,  B81B3/00

CPC classification number: H04R19/04 ,  B81B3/0086 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/04 ,  H04R7/06 ,  H04R7/18 ,  H04R19/005 ,  H04R2201/003

Abstract: An MEMS microphone comprises a substrate (100), a support portion (200), a superimposed layer (600), an upper plate (300) and a lower plate (400). The substrate (100) is provided with an opening (120) penetrating the middle thereof; the lower plate (400) is arranged above and spanning the substrate (100); the support portion (200) is fixed on the lower plate (400); the upper plate (300) is attached on the support portion (200); an accommodation cavity (500) is formed from the support portion (200), the upper plate (300) and the lower plate (400); the superimposed layer (600) is attached on an central region of the upper plate (300) or the lower plate (400), and insulation is achieved between the upper plate (300) and a lower plate (400).

公开(公告)号：US09972525B2

公开(公告)日：2018-05-15

申请号：US15547200

申请日：2015-09-24

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Hua Song ,  Jiao Wang ,  Huan Yang

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/763

CPC classification number: H01L21/76202 ,  H01L21/762 ,  H01L21/76205 ,  H01L21/76224 ,  H01L21/76227 ,  H01L21/76264 ,  H01L21/76286 ,  H01L21/763 ,  H01L21/823481

Abstract: A method for preparing a trench isolation structure, which comprises the following steps of: providing a substrate; forming an oxide layer on the substrate; successively generating an oxidation barrier layer and an ethyl orthosilicate layer on the surface of the oxide layer; etching the oxidation barrier layer and the ethyl orthosilicate layer; corroding the substrate to form a trench by using the oxidation barrier layer and the ethyl orthosilicate layer as mask layers; removing the ethyl orthosilicate layer, and oxidizing a side wall of the trench by using the oxidation barrier layer as a barrier layer; filling the trench with a polysilicon and then etching back the polysilicon, and removing the polysilicon on the surface of the oxidation barrier layer; and removing the oxidation barrier layer and the oxide layer on the surface of the substrate.

公开(公告)号：US20170069507A1

公开(公告)日：2017-03-09

申请号：US15120323

申请日：2015-04-30

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Qiang HUA ,  Yaohui ZHOU

IPC: H01L21/3105 ,  H01L21/02

CPC classification number: H01L21/31056 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76 ,  H01L21/762

Abstract: A chemical-mechanical polishing process using a silicon oxynitride anti-reflection layer (S340) includes: (S1) providing a semiconductor wafer comprising a substrate (S310), an oxidation layer (S320) formed on the substrate (S310), a silicon nitride layer (S330) formed on the oxidation layer (S320), an anti-reflection layer (S340) formed on the silicon nitride layer (S330), a trench extending through the anti-reflection layer (S340) and into the substrate (S310), and a first silicon dioxide layer (S350) filling the trench and covering the anti-reflection layer (S340); (S2) polishing the first silicon dioxide layer (S350) until the anti-reflection layer (S340) is exposed; (S3) removing the anti-reflection layer (S340) by dry etching; (S4) forming a second silicon dioxide layer (S360) on the surface of the semiconductor wafer from which the anti-reflection layer (S340) is removed; (S5) polishing the second silicon dioxide layer (S360) until the silicon nitride layer (S330) is exposed; (S6) and, removing the silicon nitride layer (S330).

Abstract translation: 使用氮氧化硅防反射层（S340）的化学机械抛光工艺包括：（S1）提供包括基板的半导体晶片（S310），形成在基板上的氧化层（S320）（S310），氮化硅 形成在氧化层上的层（S330）（S320），形成在氮化硅层上的防反射层（S340）（S330），延伸穿过防反射层（S340）并进入衬底（S310）的沟槽， 和填充该沟槽并覆盖防反射层的第一二氧化硅层（S350）（S340）; （S2）抛光第一二氧化硅层（S350），直到防反射层（S340）曝光; （S3）通过干蚀刻去除抗反射层（S340）; （S4）在去除了防反射层（S340）的半导体晶片的表面上形成第二二氧化硅层（S360） （S5）研磨第二二氧化硅层（S360），直到氮化硅层（S330）露出为止; （S6），除去氮化硅层（S330）。