公开(公告)号：US20120290117A1

公开(公告)日：2012-11-15

申请号：US13107401

申请日：2011-05-13

申请人： Jane-Yau Wang ,  Chih-Chung Chen ,  Chih-Hsien Lin

发明人： Jane-Yau Wang ,  Chih-Chung Chen ,  Chih-Hsien Lin

IPC分类号： H01L21/02

CPC分类号： H01L23/544 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming indicia on a semiconductor device package, such as laser marked or ink stamp marked indicia. The method can be performed on an apparatus, such as a production apparatus, which forms the indicia as well as performs semiconductor device trim and form operations. An embodiment of the present teachings ensures that the indicia marking process at a laser marking station does not occur simultaneously with the device trim and form operations at a trim and form station. Trim and form operations, particularly using a ram press, can impose vibrations on the laser marking station. Ensuring that laser marking does not occur simultaneously with trim and form operations removes the negative effects of vibration on the laser marking station.

摘要翻译： 一种用于在半导体器件封装上形成标记的方法，例如激光标记或墨水标记的标记。 该方法可以在形成标记的设备，例如生产设备上执行，并且执行半导体器件修整和形成操作。 本教导的一个实施例确保了在激光打标站处的标记标记过程不与设备修剪同时进行，并且在修剪和成型台处形成操作。 修剪和成型操作，特别是使用冲压机，可以在激光打标台上施加振动。 确保激光打标不会与修剪和成形操作同时发生，从而消除激光打标台上振动的负面影响。

公开(公告)号：US08242824B1

公开(公告)日：2012-08-14

申请号：US13015595

申请日：2011-01-28

申请人： Yen-Yin Huang ,  Chih-Hsien Lin ,  Chauo-Min Chen ,  Ming-Shih Yu

发明人： Yen-Yin Huang ,  Chih-Hsien Lin ,  Chauo-Min Chen ,  Ming-Shih Yu

IPC分类号： H03L7/00

CPC分类号： H03L7/0816 ,  H03K5/133 ,  H03K5/135 ,  H03L7/0814

摘要： A signal delay apparatus, including: a period digitalization circuit, for digitalizing a period of a reference clock signal to generate a digitalized reference period; a delay control signal generator, for generating a delay control signal according to the digitalized reference period, a reference frequency and a required delay indicating signal; and a delay circuit, for delaying an input signal to generate an output signal according to the required delay control signal.

摘要翻译： 一种信号延迟装置，包括：周期数字化电路，用于对参考时钟信号的周期进行数字化以产生数字化参考周期; 延迟控制信号发生器，用于根据数字化参考周期产生延迟控制信号，参考频率和所需延迟指示信号; 以及延迟电路，用于根据所需的延迟控制信号延迟输入信号以产生输出信号。

公开(公告)号：US07639801B2

公开(公告)日：2009-12-29

申请号：US11096957

申请日：2005-03-31

申请人： Shyh-Jye Jou ,  Chih-Ning Chen ,  You-Jiun Wang ,  Ju-Yuan Hsiao ,  Chih-Hsien Lin

发明人： Shyh-Jye Jou ,  Chih-Ning Chen ,  You-Jiun Wang ,  Ju-Yuan Hsiao ,  Chih-Hsien Lin

IPC分类号： H04L9/00

CPC分类号： H03K3/356156 ,  H04B2201/70707

摘要： A method of transforming a serial scrambler to a parallel scrambler, a parallel scrambler and a double-edge-triggered register with XOR operation are provided. The method transforms a serial scrambler to a parallel scrambler according to a characteristic polynomial: P ⁡ ( x ) = ∑ q = 0 N ⁢ c q ⁢ x q ⁢ ⁢ or ⁢ ⁢ b ⁡ ( i ) = ∑ q = 1 N ⁢ c q ⁢ b ⁡ ( i - q ) . The method first determines a transformation formula: b ⁡ ( kN + i ) = ∑ q = 1 N ⁢ c q ⁢ b ⁡ ( ( k - R ) ⁢ N + i + R ⁡ ( N - q ) ) according to the parameters of the characteristic polynomial. The parallel bits Bj=[bMj, bMj+1, . . . , bMj+M−2, bMj+M−1] are arranged in order. The transformation number R=2t (the initial number of t is 0) is set. The parallel bits are replaced by the transformation formula. When (k−R)N+i+R(N−q) is larger than Mj−1 in the transformation formula, 1 is added to t in the transformation formula R=2t and the transformation formula is re-counted. Finally, the XOR gates are connected to the registers according to a computed result from the transformation formula.

摘要翻译： 提供了一种将串行加扰器变换为并行扰频器，并行扰频器和具有异或运算的双边沿触发寄存器的方法。 该方法根据特征多项式将串扰扰码器转换为并行扰频器：P⁡（x）=Σq = 0 N cq xq ud或⁢b⁡（i）=Σq = 1 N cq b⁡（i-q）。 该方法首先根据下列参数确定变换公式：b⁡（kN + i）=Σq = 1 N cq b⁡（（k-R）N + i + R⁡（N-q） 特征多项式。 并行位Bj = [bMj，bMj + 1，... 。 。 ，bMj + M-2，bMj + M-1]。 转换数R = 2t（t的初始数为0）被设置。 并行位由变换公式代替。 当变换式中（k-R）N + i + R（N-q）大于Mj-1时，在转化公式R = 2t中加入1，转化公式重新计算。 最后，XOR门根据转换公式的计算结果连接到寄存器。

公开(公告)号：US07030728B2

公开(公告)日：2006-04-18

申请号：US10831848

申请日：2004-04-26

申请人： Kong-Beng Thei ,  Chih-Hsien Lin ,  Shyh-Chyi Wong

发明人： Kong-Beng Thei ,  Chih-Hsien Lin ,  Shyh-Chyi Wong

IPC分类号： H01C1/012

CPC分类号： H01L28/20 ,  H01C7/006 ,  H01C17/0656 ,  H01C17/075 ,  H01L27/0802 ,  Y10T29/49082 ,  Y10T29/49087 ,  Y10T29/49098

摘要： A resistor layout and method of forming the resistor are described which achieves improved resistor characteristics, such as resistor stability and voltage coefficient of resistance. A resistor is formed from a conducting material such as doped silicon or polysilicon. The resistor has a rectangular first resistor element, a second resistor element, a third resistor element, a fourth resistor element, and a fifth resistor element. A layer of protective dielectric is then formed over the first, second, and third resistor elements leaving the fourth and fifth resistor elements exposed. The conducting material in the exposed fourth and fifth resistor elements is then changed to a silicide, such as titanium silicide or cobalt silicide, using a silicidation process. The higher conductivity silicide forms low resistance contacts between the second and fourth resistor elements and between the third and fifth resistor elements. The second and third resistor elements are wider than the first resistor element and provide a low resistance contacts to the first resistor element, which is the main resistor element. This provides low voltage coefficient of resistance thermal process stability for the resistor.

摘要翻译： 描述了形成电阻器的电阻器布局和方法，其实现了电阻器稳定性和电阻电压系数的改善的电阻器特性。 电阻器由诸如掺杂硅或多晶硅的导电材料形成。 电阻器具有矩形的第一电阻元件，第二电阻元件，第三电阻元件，第四电阻元件和第五电阻元件。 然后在第一，第二和第三电阻器元件上形成保护电介质层，留下第四和第五电阻元件。 然后，使用硅化工艺将暴露的第四和第五电阻器元件中的导电材料改变为硅化物，例如硅化钛或硅化钴。 较高电导率的硅化物在第二和第四电阻元件之间以及第三和第五电阻器元件之间形成低电阻触点。 第二和第三电阻器元件比第一电阻器元件宽，并且向作为主电阻器元件的第一电阻器元件提供低电阻触点。 这为电阻器提供了低电阻系数的电阻热处理稳定性。

公开(公告)号：US06734079B2

公开(公告)日：2004-05-11

申请号：US10170840

申请日：2002-06-13

申请人： Chi-Feng Huang ,  Shyh-Chyi Wang ,  Chih-Hsien Lin ,  Chun-Hon Chen ,  Tien-I Bao ,  Syun-Ming Jang

发明人： Chi-Feng Huang ,  Shyh-Chyi Wang ,  Chih-Hsien Lin ,  Chun-Hon Chen ,  Tien-I Bao ,  Syun-Ming Jang

IPC分类号： H01L2120

CPC分类号： H01L28/55 ,  Y10S438/945

摘要： Within a method for fabricating a microelectronic fabrication, and the microelectronic fabrication fabricated employing the method, there is formed within the microelectronic fabrication a capacitor structure which comprises a first capacitor plate layer having formed thereupon a capacitor dielectric layer in turn having formed thereupon a second capacitor plate layer, wherein each of the foregoing layers having an exposed sidewall to thus form a series of exposed sidewalls. The capacitor structure also comprises a silicon oxide dielectric layer formed passivating the series of exposed sidewalls of the first capacitor plate layer, the capacitor dielectric layer and the second capacitor plate layer a silicon oxide dielectric layer.

摘要翻译： 在制造微电子制造的方法和使用该方法制造的微电子制造中，在微电子制造中形成电容器结构，该电容器结构包括依次形成有电容器电介质层的第一电容器板层，其上形成有第二电容器 板层，其中每个前述层具有暴露的侧壁，从而形成一系列暴露的侧壁。 电容器结构还包括形成钝化第一电容器板层的一系列暴露的侧壁，电容器介电层和第二电容器板层的氧化硅介电层的氧化硅介电层。

公开(公告)号：US20180311016A1

公开(公告)日：2018-11-01

申请号：US15499998

申请日：2017-04-28

申请人： Ming-Yuan Shao ,  Chih-Hsien Lin

发明人： Ming-Yuan Shao ,  Chih-Hsien Lin

IPC分类号： A61C8/02 ,  A61C13/15 ,  A61N5/06 ,  A61F2/46 ,  A61F2/28 ,  A61L27/24

摘要： A regeneration membrane is provided for dentistry. The traditional thin collagen is turned into a flowable and shapeable collagen gel. A photo-crosslinking agent (i.e. riboflavin (vitamin B2)) is added in a biomedical-level collagen gel to obtain the shapeable collagen gel. The shapeable collagen gel is filled in a pre-filled syringe. The shapeable collagen gel is squeezed to a destined position for paving and shaping. Then, crosslinking is processed through UV illumination for curing. Flowability is achieved for applying. After applying, solidification is finished through illumination to turn liquid into solid. Thus, a regeneration membrane is formed with biological tolerance.

公开(公告)号：US20160305743A1

公开(公告)日：2016-10-20

申请号：US14998998

申请日：2016-03-15

申请人： Yen-Chao Chen ,  Chih-Hsien Lin

发明人： Yen-Chao Chen ,  Chih-Hsien Lin

IPC分类号： F41G3/16 ,  F41G3/06 ,  F41G1/38 ,  F41G1/467 ,  H04N7/18 ,  G02B23/14

CPC分类号： F41G3/165 ,  F41G1/38 ,  F41G1/473 ,  F41G3/06 ,  F41G3/08 ,  G02B13/16 ,  G02B23/14 ,  G02B25/001 ,  H04N7/183

摘要： A trajectory prediction system for predicting a point of impact of an object shot from a ballistic device is provided. The trajectory prediction system includes an objective lens, an eyepiece lens optically coupled with the objective lens, an image sensor, a processor, and a display electrically connected to the processor and the image sensor. The image sensor, the processor, and the display are disposed between the objective lens and the eyepiece lens. When an external light reaches the image sensor through the objective lens, the image sensor transmits a first signal to the display, and the display shows an image according to the first signal. The processor calculates the trajectory of the object and transmits a second signal to the display, and the display simultaneously shows the image and at least one predictive point of impact according to the first and second signals.

摘要翻译： 提供了一种用于预测从弹道装置拍摄的物体的撞击点的轨迹预测系统。 轨迹预测系统包括物镜，与物镜光学耦合的目镜，图像传感器，处理器和电连接到处理器和图像传感器的显示器。 图像传感器，处理器和显示器设置在物镜和目镜之间。 当外部光通过物镜到达图像传感器时，图像传感器将第一信号发送到显示器，并且显示器根据第一信号显示图像。 处理器计算对象的轨迹并向显示器发送第二信号，并且显示器同时根据第一和第二信号显示图像和至少一个影响预测点。

公开(公告)号：US08618640B2

公开(公告)日：2013-12-31

申请号：US13194033

申请日：2011-07-29

申请人： Hsiang-Tai Lu ,  Chih-Hsien Lin ,  Meng-Lin Chung

发明人： Hsiang-Tai Lu ,  Chih-Hsien Lin ,  Meng-Lin Chung

IPC分类号： H01L23/552

CPC分类号： H01L21/265 ,  H01L21/76802 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/5225 ,  H01L23/552 ,  H01L2224/16

摘要： A passive interposer apparatus with a shielded through silicon via (TSV) configuration is disclosed. The apparatus includes a p-doped substrate, wherein at least an upper portion of the p-doped substrate is heavily p-doped. An interlayer dielectric layer (ILD) is disposed over the upper portion of the p-doped substrate. A plurality of through silicon vias (TSVs) are formed through the ILD and the p-doped substrate. A plurality of shielding lines disposed between the TSVs electrically couple respective second metal contact pads to the upper portion of the p-doped substrate.

摘要翻译： 公开了一种具有屏蔽硅通孔（TSV）配置的无源中介器。 该装置包括p掺杂衬底，其中至少p掺杂衬底的上部是高度p掺杂的。 层间电介质层（ILD）设置在p掺杂衬底的上部上。 通过ILD和p掺杂衬底形成多个穿通硅通孔（TSV）。 设置在TSV之间的多个屏蔽线将各个第二金属接触焊盘电耦合到p掺杂衬底的上部。

公开(公告)号：US20120194242A1

公开(公告)日：2012-08-02

申请号：US13015595

申请日：2011-01-28

申请人： Yen-Yin Huang ,  Chih-Hsien Lin ,  Chauo-Min Chen ,  Ming-Shih Yu

发明人： Yen-Yin Huang ,  Chih-Hsien Lin ,  Chauo-Min Chen ,  Ming-Shih Yu

IPC分类号： H03L7/24 ,  H03H11/26

CPC分类号： H03L7/0816 ,  H03K5/133 ,  H03K5/135 ,  H03L7/0814

摘要： A signal delay apparatus, including: a period digitalization circuit, for digitalizing a period of a reference clock signal to generate a digitalized reference period; a delay control signal generator, for generating a delay control signal according to the digitalized reference period, a reference frequency and a required delay indicating signal; and a delay circuit, for delaying an input signal to generate an output signal according to the required delay control signal.

摘要翻译： 一种信号延迟装置，包括：周期数字化电路，用于对参考时钟信号的周期进行数字化以产生数字化参考周期; 延迟控制信号发生器，用于根据数字化参考周期产生延迟控制信号，参考频率和所需延迟指示信号; 以及延迟电路，用于根据所需的延迟控制信号延迟输入信号以产生输出信号。

公开(公告)号：US07897505B2

公开(公告)日：2011-03-01

申请号：US11727133

申请日：2007-03-23

申请人： Chung-Chi Ko ,  Lih-Ping Li ,  Yung-Cheng Lu ,  Hui-Lin Chang ,  Chih-Hsien Lin

发明人： Chung-Chi Ko ,  Lih-Ping Li ,  Yung-Cheng Lu ,  Hui-Lin Chang ,  Chih-Hsien Lin

IPC分类号： H01L21/4763 ,  H01L21/00

CPC分类号： H01L21/31633 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835

摘要： A novel method for enhancing interface adhesion between adjacent dielectric layers, particularly between an etch stop layer and an overlying dielectric layer having a low dielectric constant (k) in the formation of metal interconnects during the fabrication of integrated circuits on semiconductor wafer substrates. The method may include providing a substrate, providing an etch stop layer on the substrate, providing an oxygen-rich dielectric pre-layer on the etch stop layer and providing a major dielectric layer on the oxygen-rich dielectric pre-layer. Metal interconnects are then formed in the dielectric layers. The oxygen-rich dielectric pre-layer between the etch stop layer and the upper dielectric layer prevents or minimizes peeling and cracking of the layers induced by stresses that are caused by chemical mechanical planarization of metal layers and/or chip packaging.

摘要翻译： 一种新颖的方法，用于在半导体晶片衬底上的集成电路制造过程中，在金属互连的形成过程中，增强相邻电介质层之间的界面附着力，特别是在蚀刻停止层和具有低介电常数（k）的上覆电介质层之间。 该方法可以包括提供衬底，在衬底上提供蚀刻停止层，在蚀刻停止层上提供富氧介电预置层，并在富氧电介质预层上提供主要电介质层。 然后在电介质层中形成金属互连。 在蚀刻停止层和上部电介质层之间的富氧介电预层防止或最小化由金属层和/或芯片封装的化学机械平坦化引起的应力引起的层的剥离和破裂。