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    Buffer circuit with data bit inversion
    32.
    发明授权
    Buffer circuit with data bit inversion 有权

    公开(公告)号：US12067285B2

    公开(公告)日：2024-08-20

    申请号：US18093258

    申请日：2023-01-04

    Applicant: Rambus Inc.

    Inventor： Scott C. Best

    IPC: G06F3/06 ,  G11C7/10 ,  G11C5/04

    CPC classification number: G06F3/0656 ,  G06F3/0626 ,  G06F3/0673 ,  G11C7/1006 ,  G11C5/04

    Abstract: A buffer circuit includes a primary interface, a secondary interface, and an encoder/decoder circuit. The primary interface is configured to communicate on an n-bit channel, wherein n parallel bits on the n-bit channel are coded using data bit inversion (DBI). The secondary interface is configured to communicate with a plurality of integrated circuit devices on a plurality of m-bit channels, each m-bit channel transmitting m parallel bits without using DBI. And the encoder/decoder circuit is configured to translate data words between the n-bit channel of the primary interface and the plurality of m-bit channels of the secondary interface.

    UNSUCCESSFUL WRITE RETRY BUFFER
    34.
    发明公开
    UNSUCCESSFUL WRITE RETRY BUFFER 审中-公开

    公开(公告)号：US20240273038A1

    公开(公告)日：2024-08-15

    申请号：US18586867

    申请日：2024-02-26

    Applicant: Rambus Inc.

    Inventor： Hongzhong ZHENG ,  Brent Haukness

    IPC: G06F13/16 ,  G06F5/14

    CPC classification number: G06F13/1626 ,  G06F5/14

    Abstract: A memory module includes at least two memory devices. Each of the memory devices perform verify operations after attempted writes to their respective memory cores. When a write is unsuccessful, each memory device stores information about the unsuccessful write in an internal write retry buffer. The write operations may have only been unsuccessful for one memory device and not any other memory devices on the memory module. When the memory module is instructed, both memory devices on the memory module can retry the unsuccessful memory write operations concurrently. Both devices can retry these write operations concurrently even though the unsuccessful memory write operations were to different addresses.

    AREA-EFFICIENT, WIDTH-ADJUSTABLE SIGNALING INTERFACE
    35.
    发明公开
    AREA-EFFICIENT, WIDTH-ADJUSTABLE SIGNALING INTERFACE 审中-公开

    公开(公告)号：US20240265953A1

    公开(公告)日：2024-08-08

    申请号：US18581694

    申请日：2024-02-20

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware

    IPC: G11C7/10

    CPC classification number: G11C7/1012 ,  G11C7/1045 ,  G11C7/1087 ,  G11C2207/105

    Abstract: A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be intercoupled in different groups to effect the lateral data transfer required in different interface width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure.

    Multiple precision memory system
    38.
    发明授权
    Multiple precision memory system 有权

    公开(公告)号：US12026104B2

    公开(公告)日：2024-07-02

    申请号：US17438844

    申请日：2020-03-19

    Applicant: Rambus Inc.

    Inventor： Thomas Vogelsang ,  Craig E. Hampel

    IPC: G06F13/16 ,  G06F7/483

    CPC classification number: G06F13/1605 ,  G06F7/483

    Abstract: Space in a memory is allocated based on the highest used precision. When the maximum used precision is not being used, the bits required for that particular precision level (e.g., floating point format) are transferred between the processor and the memory while the rest are not. A given floating point number is distributed over non-contiguous addresses. Each portion of the given floating point number is located at the same offset within the access units, groups, and/or memory arrays. This allows a sequencer in the memory device to successively access a precision dependent number of access units, groups, and/or memory arrays without receiving additional requests over the memory channel.

    STRUCTURE FOR DELIVERING POWER
    40.
    发明公开
    STRUCTURE FOR DELIVERING POWER 审中-公开

    公开(公告)号：US20240215149A1

    公开(公告)日：2024-06-27

    申请号：US18535775

    申请日：2023-12-11

    Applicant: Rambus Inc.

    Inventor： Kyung Suk Oh ,  Ralf M. Schmitt ,  Yijong Feng

    IPC: H05K1/02 ,  H01B5/02 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

    CPC classification number: H05K1/0216 ,  H01B5/02 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5286 ,  H01L23/5223 ,  H01L2924/0002

    Abstract: A structure for delivering power is described. In some embodiments, the structure can include conductors disposed on two or more layers. Specifically, the structure can include a first set of interdigitated conductors disposed on a first layer and oriented substantially along an expected direction of current flow. At least one conductor in the first set of interdigitated conductors may be maintained at a first voltage, and at least one conductor in the first set of interdigitated conductors may be maintained at a second voltage, wherein the second voltage is different from the first voltage. The structure may further include a conducting structure disposed on a second layer, wherein the second layer is different from the first layer, and wherein at least one conductor in the conducting structure is maintained at the first voltage.

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