公开(公告)号：US20060268012A1

公开(公告)日：2006-11-30

申请号：US11498595

申请日：2006-08-03

Applicant: Alexander MacInnis ,  Chengfuh Tang ,  Xiaodong Xie ,  Greg Kranawetter ,  Vivian Hsiun ,  Francis Cheung ,  Sandeep Bhatia ,  Ramanujan Valmiki ,  Sathish Kumar

Inventor： Alexander MacInnis ,  Chengfuh Tang ,  Xiaodong Xie ,  Greg Kranawetter ,  Vivian Hsiun ,  Francis Cheung ,  Sandeep Bhatia ,  Ramanujan Valmiki ,  Sathish Kumar

IPC: G09G5/00

CPC classification number: H04N9/641 ,  G06T9/007 ,  G09G5/001 ,  G09G5/008 ,  G09G5/02 ,  G09G5/024 ,  G09G5/026 ,  G09G5/06 ,  G09G5/12 ,  G09G5/14 ,  G09G5/28 ,  G09G5/346 ,  G09G5/36 ,  G09G5/363 ,  G09G2310/0224 ,  G09G2320/0247 ,  G09G2340/02 ,  G09G2340/0407 ,  G09G2340/10 ,  G09G2340/125 ,  G09G2350/00 ,  G09G2360/02 ,  G09G2360/121 ,  G09G2360/125 ,  G09G2360/126 ,  G09G2360/128 ,  H04N5/14 ,  H04N5/4401 ,  H04N5/44504 ,  H04N5/44508 ,  H04N5/45 ,  H04N5/46 ,  H04N7/0135 ,  H04N9/45 ,  H04N11/00 ,  H04N11/143 ,  H04N11/20 ,  H04N11/22 ,  H04N21/42653 ,  H04N21/42692 ,  H04N21/4305 ,  H04N21/4316 ,  H04N21/4345 ,  H04N21/4348 ,  H04N21/440218 ,  H04N21/4435 ,  H04N21/8146

Abstract: A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.

Abstract translation: 视频，音频和图形系统使用多个传输处理器来接收带内和带外MPEG传输流，以执行PID和部分滤波以及DVB和DES解密，并对其进行解复用。 该系统将PES处理成数字音频，MPEG视频和消息数据。 该系统能够同时解码多个MPEG SLICE。 图形窗口并行混合，并使用alpha混合与视频混合。 在图形处理期间，单端口SRAM被等价地用作双端口SRAM。 视频可以包括模拟视频，例如NTSC / PAL / SECAM / S视频和数字视频，例如SDTV或HDTV格式的MPEG-2视频。 该系统具有减小的存储模式，其中仅在解码期间视频图像在水平方向上减少一半。 该系统能够接收和处理数字音频信号，如MPEG第1层和第2层音频和杜比AC-3音频以及PCM音频信号。 该系统包括一个内存控制器。 该系统包括系统桥接控制器，用于将CPU与系统内部的设备以及包括PCI设备和诸如RAM，ROM和闪存设备的I / O设备的外围设备连接。 该系统能够在高清（HD）模式和标准清晰度（SD）模式下显示视频和图形。 该系统可以在转换HDTV视频的同时输出HDTV视频，并提供具有SDTV格式或另一HDTV格式的另一输出。

公开(公告)号：US20060093225A1

公开(公告)日：2006-05-04

申请号：US10977864

申请日：2004-10-29

Applicant: Sandeep Bhatia ,  Srinivasa Mogathala Reddy ,  Sivugururaman Mahadevan

Inventor： Sandeep Bhatia ,  Srinivasa Mogathala Reddy ,  Sivugururaman Mahadevan

IPC: G06K9/36

CPC classification number: H04N19/59 ,  H04N19/428 ,  H04N19/44 ,  H04N19/61

Abstract: Presented herein are systems, methods, and apparatus for simultaneously providing full size video and massively scaled down video using inconification. In one embodiment, there is presented a method for providing a video output. The method comprises decoding an encoded picture, thereby resulting in a decoded picture; reducing the decoded picture, thereby resulting in a reduced picture; storing the reduced picture; and encoding the reduced picture, thereby resulting in a synthetic picture.

公开(公告)号：US20050286639A1

公开(公告)日：2005-12-29

申请号：US10874634

申请日：2004-06-23

Applicant: Gaurav Aggarwal ,  M.K. Subramanian ,  Sandeep Bhatia ,  Santosh Savekar ,  K. Shivapirakasan

Inventor： Gaurav Aggarwal ,  M.K. Subramanian ,  Sandeep Bhatia ,  Santosh Savekar ,  K. Shivapirakasan

IPC: H04B1/66 ,  H04N7/12 ,  H04N11/02 ,  H04N11/04

CPC classification number: H04N19/577 ,  H04N19/423 ,  H04N19/61

Abstract: Presented herein are systems and methods for pause and freeze functions for digital video streams. A particular picture is displayed for a plurality of video display periods. A next picture is displayed at the video display period immediately following the plurality of video display periods, the next picture immediately following the particular picture in a display order. A system clock reference is loaded with a time stamp associated with the next picture when displaying the next picture.

Abstract translation: 这里提出了用于数字视频流的暂停和冻结功能的系统和方法。 针对多个视频显示周期显示特定图像。 在多个视频显示周期之后的视频显示时段显示下一个图像，紧接在特定图像之后的下一个图像以显示顺序显示。 当显示下一张照片时，系统时钟参考装载有与下一张照片相关联的时间戳。

公开(公告)号：US20050175082A1

公开(公告)日：2005-08-11

申请号：US11025327

申请日：2004-12-29

Applicant: Jason Herrick ,  Darren Neuman ,  Greg Kranawetter ,  Sandeep Bhatia

Inventor： Jason Herrick ,  Darren Neuman ,  Greg Kranawetter ,  Sandeep Bhatia

IPC: H04N7/01

CPC classification number: H04N19/46

Abstract: A system and method that support display of video fields using related data encoded in data structures. Each data structure is associated with one video field and contains all the information associated with the display of the video field. The data structure is encoded with the video field that is displayed exactly one field prior to the field associated with the data structure. In an embodiment of the present invention, the data structure contains all the information associated with the display of a video field, regardless of whether certain data changes from one field to the next.

Abstract translation: 支持使用在数据结构中编码的相关数据来显示视频场的系统和方法。 每个数据结构与一个视频字段相关联并且包含与视频字段的显示相关联的所有信息。 数据结构使用在与数据结构相关联的字段之前正好显示一个字段的视频字段进行编码。 在本发明的实施例中，数据结构包含与视频字段的显示相关联的所有信息，而不管特定数据是否从一个字段改变到下一个字段。

公开(公告)号：US20050028220A1

公开(公告)日：2005-02-03

申请号：US10791686

申请日：2004-03-03

Applicant: David Baer ,  Jeff Tingley ,  Aleksandr Movshovich ,  Brad Grossman ,  Brian Schoner ,  Chengfuh Tang ,  Chuck Monahan ,  Darren Neuman ,  David Wu ,  Francis Cheung ,  Greg Kranawetter ,  Hoang Nhu ,  Hsien-Chih Tseng ,  Iue-Shuenn Chen ,  James Sweet ,  Jeffrey Bauch ,  Keith Klingler ,  Patrick Law ,  Rajesh Mamidwar ,  Dan Simon ,  Sang Tran ,  Shawn Johnson ,  Steven Jaffe ,  Thu Nguyen ,  Ut Nguyen ,  Yao-Hua Tseng ,  Brad Delanghe ,  Ben Giese ,  Jason Demas ,  Lakshman Ramakrishnan ,  Sandeep Bhatia ,  Guang-Ting Shih ,  Tracy Denk

Inventor： David Baer ,  Jeff Tingley ,  Aleksandr Movshovich ,  Brad Grossman ,  Brian Schoner ,  Chengfuh Tang ,  Chuck Monahan ,  Darren Neuman ,  David Wu ,  Francis Cheung ,  Greg Kranawetter ,  Hoang Nhu ,  Hsien-Chih Tseng ,  Iue-Shuenn Chen ,  James Sweet ,  Jeffrey Bauch ,  Keith Klingler ,  Patrick Law ,  Rajesh Mamidwar ,  Dan Simon ,  Sang Tran ,  Shawn Johnson ,  Steven Jaffe ,  Thu Nguyen ,  Ut Nguyen ,  Yao-Hua Tseng ,  Brad Delanghe ,  Ben Giese ,  Jason Demas ,  Lakshman Ramakrishnan ,  Sandeep Bhatia ,  Guang-Ting Shih ,  Tracy Denk

IPC: H04N5/44 ,  H04N5/445 ,  H04N5/46 ,  H04N5/913 ,  H04N7/035 ,  H04N3/27 ,  H04N7/173 ,  H04N11/06

CPC classification number: H04N21/426 ,  H04N5/4401 ,  H04N5/44504 ,  H04N5/46 ,  H04N7/035 ,  H04N21/4263 ,  H04N21/4305 ,  H04N2005/91364

Abstract: A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.

Abstract translation: 公开了一种提供用于在单个集成电路芯片上提供电视功能的成本有效方法的芯片上的电视（TVOC）系统。 TVOC包括以各种输入和输出格式接收和显示电视信号所必需的功能。 TVOC可用于有线和卫星电视的机顶盒，或直接在电视机内使用。 所提供的所有功能可以在单个集成电路上提供。 TVOC包括数据传输模块，IF解调器，数字音频引擎，模拟音频引擎，数字视频引擎和模拟视频引擎。 TVOC还包括三套接口，包括输出接口，控制接口和辅助接口。 其他特征和实施例提供增强的功能和提高的效率。

公开(公告)号：US20050018775A1

公开(公告)日：2005-01-27

申请号：US10892897

申请日：2004-07-16

Applicant: Mk Subramanian ,  Sandeep Bhatia ,  Santosh Savekar ,  Gaurav Aggarwal ,  K. Shivapirakasan

Inventor： Mk Subramanian ,  Sandeep Bhatia ,  Santosh Savekar ,  Gaurav Aggarwal ,  K. Shivapirakasan

IPC: H04J3/00 ,  H04N7/12 ,  H04N7/173 ,  H04N7/62 ,  H04N11/02 ,  H04N11/04

CPC classification number: H04N21/44004 ,  H04N21/4307

Abstract: Described herein is a system and method for audio visual synchronization. The picture are displayed by receiving an identifier, said identifier associated with a frame buffer storing a picture; extracting a presentation time stamp associated with the picture, wherein the picture is associated with a time stamp; comparing a local time clock value to the presentation time stamp; determining that the picture is mature for presentation if the presentation time stamp exceeds the local time clock value by less than a first predetermined threshold; and determining that the picture is mature for presentation if the local time clock value exceeds the presentation time stamp by less than a second predetermined threshold.

Abstract translation: 这里描述了一种用于视听同步的系统和方法。 通过接收标识符显示图像，所述标识符与存储图像的帧缓冲器相关联; 提取与所述图片相关联的呈现时间戳，其中所述图片与时间戳相关联; 将本地时钟值与演示时间戳进行比较; 如果所述呈现时间戳超过所述本地时间时钟值小于第一预定阈值，则确定所述图片是成熟的; 以及如果所述本地时间时钟值超过所述呈现时间戳小于第二预定阈值，则确定所述图片是否成熟以进行呈现。

公开(公告)号：US06636222B1

公开(公告)日：2003-10-21

申请号：US09641936

申请日：2000-08-18

Applicant: Ramanujan K. Valmiki ,  Sandeep Bhatia

Inventor： Ramanujan K. Valmiki ,  Sandeep Bhatia

IPC: G06F1580

CPC classification number: G06T9/007 ,  G06F15/80 ,  G09G5/001 ,  G09G5/02 ,  G09G5/024 ,  G09G5/026 ,  G09G5/06 ,  G09G5/12 ,  G09G5/14 ,  G09G5/28 ,  G09G5/346 ,  G09G5/36 ,  G09G5/363 ,  G09G2300/0408 ,  G09G2310/0224 ,  G09G2320/0247 ,  G09G2340/02 ,  G09G2340/0407 ,  G09G2340/0428 ,  G09G2340/06 ,  G09G2340/10 ,  G09G2340/12 ,  G09G2340/125 ,  G09G2360/02 ,  G09G2360/121 ,  G09G2360/125 ,  G09G2360/126 ,  G09G2360/128 ,  H04N5/126 ,  H04N5/14 ,  H04N5/4401 ,  H04N5/44504 ,  H04N5/44508 ,  H04N5/44591 ,  H04N5/45 ,  H04N5/46 ,  H04N7/00 ,  H04N7/0135 ,  H04N9/45 ,  H04N9/641 ,  H04N9/642 ,  H04N11/143 ,  H04N11/20 ,  H04N19/42 ,  H04N19/423 ,  H04N19/436 ,  H04N19/44 ,  H04N19/61 ,  H04N21/42204 ,  H04N21/42653 ,  H04N21/4305 ,  H04N21/4316 ,  H04N21/434 ,  H04N21/4438 ,  H04N21/47 ,  Y10S502/506

Abstract: A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video data. The video decoder includes multiple row decoding engines for decoding the MPEG-2 video data. Each row decoding engine concurrently decodes two or more rows of the MPEG-2 video data. The row decoding engines have a pipelined architecture for concurrently decoding multiple rows of MPEG-2 video data. The video decoder may be integrated on an integrated circuit chip with other video and graphics system components such as transport processors for receiving one or more compressed data streams and for extracting video data, and a video compositor for blending processed video data with graphics.

Abstract translation: 视频和图形系统处理包括模拟视频（例如NTSC / PAL / SECAM / S视频）和数字视频（例如，以SDTV或HDTV格式的MPEG-2视频）的视频数据。 视频和图形系统包括视频解码器，其能够同时解码MPEG-2视频数据的多个SLICE。 视频解码器包括用于解码MPEG-2视频数据的多行解码引擎。 每行解码引擎同时解码MPEG-2视频数据的两行或多行。 行解码引擎具有用于同时解码多行MPEG-2视频数据的流水线架构。 视频解码器可以集成在具有其他视频和图形系统组件的集成电路芯片上，诸如用于接收一个或多个压缩数据流并用于提取视频数据的传输处理器，以及用于将经处理的视频数据与图形混合的视频合成器。

公开(公告)号：US5882618A

公开(公告)日：1999-03-16

申请号：US845849

申请日：1997-04-28

Applicant: Sandeep Bhatia ,  Metin Gezer

Inventor： Sandeep Bhatia ,  Metin Gezer

IPC: C01C3/02 ,  C01C3/08

CPC classification number: C01C3/0212 ,  C01C3/0216

Abstract: Provided is a process for the production of hydrogen cyanide by reacting methane, ammonia and oxygen in the presence of a catalyst. The process, more specifically, comprises first establishing a temperature for the catalyst in the reaction using air as a source for oxygen. This essentially establishes the gauze temperature of the plant. Additional oxygen is then provided to the reaction to provide oxygen enrichment of the reaction feed, while also adjusting the amount of ammonia and methane reactants in the reaction feed such that the volume percent of the ammonia and methane is above the upper flammability limit and the temperature of catalyst is maintained within 50.degree. C. of the temperature of the catalyst originally established as the fixed gauze temperature of the plant. The process of the present invention allows one to increase production of hydrogen cyanide while maintaining safe operation and not sacrificing catalyst performance in return. In particular, the process of the present invention has applicability to existing plants which need to be improved with regard to hydrogen cyanide production. The process would allow one to take the existing plant, optimize production, capacity and selectivity, while operating safely without adversely affecting catalyst performance.

Abstract translation: 提供了一种在催化剂存在下使甲烷，氨和氧反应生成氰化氢的方法。 更具体地说，该方法包括首先使用空气作为氧气的来源建立反应中催化剂的温度。 这基本上建立了植物的纱布温度。 然后向反应物中提供额外的氧以提供反应进料的氧气富集，同时还调节反应进料中的氨和甲烷反应物的量，使得氨和甲烷的体积百分比高于上限的可燃性极限和温度 的催化剂保持在最初建立为工厂的固定纱布温度的催化剂的温度的50℃内。 本发明的方法允许在保持安全操作的同时增加氰化氢的产生，而不会牺牲催化剂性能。 特别地，本发明的方法适用于在氰化氢生产方面需要改进的现有设备。 该过程将允许一个人采用现有的设备，优化生产，容量和选择性，同时安全运行，而不会对催化剂性能造成不利影响。

公开(公告)号：US08676025B2

公开(公告)日：2014-03-18

申请号：US10174355

申请日：2002-06-18

Applicant: Jason Demas ,  Marcus Kellerman ,  Sandeep Bhatia ,  Srinivasa Mogathala Prabhakara Reddy ,  Sherman (Xuemin) Chen ,  Vijayanand Aralaguppe ,  Girish Raghunath Hulamani ,  Pramod Chandraiah ,  Ghanashayam Bailwal

Inventor： Jason Demas ,  Marcus Kellerman ,  Sandeep Bhatia ,  Srinivasa Mogathala Prabhakara Reddy ,  Sherman (Xuemin) Chen ,  Vijayanand Aralaguppe ,  Girish Raghunath Hulamani ,  Pramod Chandraiah ,  Ghanashayam Bailwal

IPC: H04N5/935 ,  H04N5/94 ,  H04N5/76 ,  H04N9/79 ,  H04N9/804

CPC classification number: G11B27/10 ,  G11B27/005 ,  H04N5/76 ,  H04N5/783 ,  H04N5/935 ,  H04N5/94 ,  H04N9/79 ,  H04N9/7921 ,  H04N9/8042 ,  H04N9/87 ,  H04N19/44 ,  H04N21/4147 ,  H04N21/4305 ,  H04N21/4341 ,  H04N21/8455

Abstract: Systems and methods that provide time-based management for MPEG decoding are provided. In one example, a method for live decoding in a personal video recorder system includes the steps of receiving at least one data packet; determining at least one program clock reference (PCR) using the at least one data packet; and locking a timing mechanism to the at least one determined PCR.

Abstract translation: 提供了为MPEG解码提供基于时间的管理的系统和方法。 在一个示例中，个人录像机系统中的实时解码方法包括以下步骤：接收至少一个数据包; 使用所述至少一个数据分组来确定至少一个程序时钟参考（PCR）; 以及将定时机制锁定到所述至少一个确定的PCR。

公开(公告)号：USRE44479E1

公开(公告)日：2013-09-03

申请号：US13494363

申请日：2012-06-12

Applicant: Qi Wang ,  Ankur Gupta ,  Pinhong Chen ,  Christina Chu ,  Manish Pandey ,  Huan-Chih Tsai ,  Sandeep Bhatia ,  Yonghoa Chen ,  Steven Sharp ,  Vivek Chickermane ,  Patrick Gallagher ,  Mitchell W. Hines

Inventor： Qi Wang ,  Ankur Gupta ,  Pinhong Chen ,  Christina Chu ,  Manish Pandey ,  Huan-Chih Tsai ,  Sandeep Bhatia ,  Yonghoa Chen ,  Steven Sharp ,  Vivek Chickermane ,  Patrick Gallagher ,  Mitchell W. Hines

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5022 ,  G06F17/5081 ,  G06F2217/78

Abstract: A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.

Abstract translation: 一种将功率控制电路添加到RTL和网表级别中的每一个处的电路设计的方法，包括：划分所述电路设计内的多个电源域; 指定多个功率模式，每个功率模式对应于多个划分的功率域的开/关状态的不同组合; 并定义相对于各自的功率域的隔离行为。