利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

182 条记录 (耗时 0.015 秒)

    Methods of forming silicon dioxide layers, and methods of forming trench isolation regions
    31.
    发明授权
    Methods of forming silicon dioxide layers, and methods of forming trench isolation regions 有权
    形成二氧化硅层的方法以及形成沟槽隔离区的方法

    公开(公告)号：US07211499B2

    公开(公告)日：2007-05-01

    申请号：US11362455

    申请日：2006-02-23

    申请人： Sujit Sharan ,  Gurtej S. Sandhu

    发明人： Sujit Sharan ,  Gurtej S. Sandhu

    IPC分类号： H01L21/76

    CPC分类号： H01L21/02164 ,  C23C16/045 ,  C23C16/402 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/76224

    摘要： A method of forming a silicon dioxide layer includes forming a high density plasma proximate a substrate, the plasma comprising silicon dioxide precursors; forming silicon dioxide from the precursors, the silicon dioxide being deposited over the substrate at a deposition rate; and while depositing, etching the deposited silicon dioxide with the plasma at an etch rate; a ratio of the deposition rate to the etch rate being at least about 4:1. Another method includes forming a high density plasma proximate a substrate; flowing gases into the plasma, at least some of the gases forming silicon dioxide; depositing the silicon dioxide formed from the gases over the substrate; and while depositing the silicon dioxide, maintaining a temperature of the substrate at greater than or equal to about 500° C. As an alternative, the method may include not cooling the substrate with a coolant gas while depositing the silicon dioxide.

    摘要翻译： 形成二氧化硅层的方法包括在基底附近形成高密度等离子体，所述等离子体包含二氧化硅前体; 从前体形成二氧化硅，二氧化硅以沉积速率沉积在衬底上; 并且在沉积时以蚀刻速率用等离子体蚀刻沉积的二氧化硅; 沉积速率与蚀刻速率的比率为至少约4:1。 另一种方法包括在基底附近形成高密度等离子体; 流入气体进入等离子体，形成二氧化硅的至少一些气体; 将由气体形成的二氧化硅沉积在衬底上; 并且同时沉积二氧化硅，将基底的温度保持在大于或等于约500℃。作为替代方案，该方法可以包括在沉积二氧化硅的同时不用冷却剂气体冷却基底。

    SYSTEM AND METHOD FOR DETECTING FLOW IN A MASS FLOW CONTROLLER
    32.
    发明申请
    SYSTEM AND METHOD FOR DETECTING FLOW IN A MASS FLOW CONTROLLER 审中-公开

    公开(公告)号：US20060223204A1

    公开(公告)日：2006-10-05

    申请号：US11421704

    申请日：2006-06-01

    申请人： Gurtej Sandhu ,  Sujit Sharan ,  Neal Rueger ,  Allen Mardian

    发明人： Gurtej Sandhu ,  Sujit Sharan ,  Neal Rueger ,  Allen Mardian

    IPC分类号： H01L21/66 ,  G01R31/26

    CPC分类号： G01F1/40 ,  G01F1/42 ,  G01P13/0006 ,  G01P13/0013 ,  G01P13/0033 ,  G05D7/0635 ,  Y10T137/0396 ,  Y10T137/7722 ,  Y10T137/775 ,  Y10T137/8242

    摘要： Systems and methods are provided for detecting flow in a mass flow controller (MFC). The position of a gate in the MFC is sensed or otherwise determined to monitor flow through the MFC and to immediately or nearly immediately detect a flow failure. In one embodiment of the present invention, a novel MFC is provided. The MFC includes an orifice, a mass flow control gate, an actuator and a gate position sensor. The actuator moves the control gate to control flow through the orifice. The gate position sensor determines the gate position and/or gate movement to monitor flow and immediately or nearly immediately detect a flow failure. According to one embodiment of the present invention, the gate position sensor includes a transmitter for transmitting a signal and a receiver for receiving the signal such that the receiver provides an indication of the position of the gate based on the signal received. Other embodiments of the gate position sensor are described herein, as well as systems and methods that incorporate the novel MFC within a semiconductor manufacturing process.

    Methods of forming an electrically conductive line
    36.
    发明授权
    Methods of forming an electrically conductive line 失效
    形成导电线的方法

    公开(公告)号：US06977221B2

    公开(公告)日：2005-12-20

    申请号：US10895483

    申请日：2004-07-20

    申请人： Gurtej S. Sandhu ,  Sujit Sharan

    发明人： Gurtej S. Sandhu ,  Sujit Sharan

    IPC分类号： H01L21/20 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/44

    CPC分类号： H01L21/02667 ,  C30B1/02 ,  C30B29/34 ,  H01L21/2022 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/32053 ,  H01L29/7842

    摘要： The invention includes a method of forming a crystalline phase material which includes providing a stress inducing material within or operatively adjacent a crystalline material of a first crystalline phase and annealing the crystalline material of the first crystalline phase to transform it to a second crystalline phase. The stress inducing material induces compressive stress within the first crystalline phase during the anneal to produce a more dense second crystalline phase. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials for providing into layers are Ge, W and Co. Example and preferred crystalline phase materials having two phases are refractory metal silicides, such as TiSix. The invention additionally includes incorporating the crystalline phase material into a conductive line.

    摘要翻译： 本发明包括一种形成结晶相材料的方法，该方法包括在第一结晶相的结晶材料内或与第一结晶相结晶材料相接触地提供应力诱导材料，并退火第一结晶相的晶体材料以将其转变成第二结晶相。 应力诱导材料在退火期间在第一结晶相内引起压缩应力以产生更致密的第二结晶相。 示例性压缩应力诱导层包括SiO 2和Si 3 N 4，而用于提供层的应力诱导材料是Ge，W和Co 具有两相的实例和优选结晶相材料是难熔金属硅化物，例如TiSi x Si。 本发明另外包括将结晶相材料结合到导电线中。

    Plasma enhanced chemical vapor deposition methods and semiconductor processing methods of forming layers and shallow trench isolation regions
    38.
    发明申请
    Plasma enhanced chemical vapor deposition methods and semiconductor processing methods of forming layers and shallow trench isolation regions 审中-公开
    等离子体增强化学气相沉积方法和形成层和浅沟槽隔离区的半导体加工方法

    公开(公告)号：US20050079731A1

    公开(公告)日：2005-04-14

    申请号：US10620426

    申请日：2003-07-17

    申请人： Sujit Sharan ,  Gurtej Sandhu

    发明人： Sujit Sharan ,  Gurtej Sandhu

    IPC分类号： C23C16/04 ,  C23C16/40 ,  H01L21/316 ,  H01L21/762 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/02164 ,  C23C16/045 ,  C23C16/402 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/76224

    摘要： In accordance with an aspect of the invention, a substrate is placed within a plasma enhanced chemical vapor deposition reactor. A plurality of reactant gases are provided within the reactor proximate the substrate under high density plasma conditions effective to form a layer on the substrate. The conditions result in etching portions of the layer during its formation and thereby include a deposition to etch ratio of forming the layer. During the forming, the conditions are changed to change the deposition to etch ratio. In another aspect of the invention, the invention includes a semiconductor processing method of forming shallow trench isolation regions within a semiconductive substrate. Isolation trenches are formed within the semiconductive substrate. The substrate is provided within a plasma enhanced chemical vapor deposition reactor. A silane containing gas, an oxygen containing gas and an inert gas are injected into the reactor under high density plasma conditions effective to form a predominate SiO2 comprising layer on the substrate to overfill the trenches. The conditions result in etching of portions of the layer during its formation and thereby includes a deposition to etch ratio of the forming SiO2 comprising layer. During the forming, the conditions are changed to change the deposition to etch ratio.

    摘要翻译： 根据本发明的一个方面，将衬底放置在等离子体增强化学气相沉积反应器内。 在高密度等离子体条件下，靠近基板的反应器内提供多个反应气体，以有效地在基板上形成一层。 条件导致在其形成期间蚀刻该层的部分，从而包括形成该层的沉积 - 蚀刻比。 在成形期间，改变条件以改变沉积到蚀刻比。 在本发明的另一方面，本发明包括在半导体衬底内形成浅沟槽隔离区的半导体处理方法。 绝缘沟槽形成在半导体衬底内。 衬底设置在等离子体增强化学气相沉积反应器内。 将含硅烷的气体，含氧气体和惰性气体在高密度等离子体条件下注入到反应器中，在等离子体条件下有效地在衬底上形成主要的含SiO 2的层，以使填充沟槽。 条件导致在其形成期间蚀刻该层的部分，从而包括形成SiO 2的层的沉积蚀刻比。 在成形期间，改变条件以改变沉积到蚀刻比。

    Protective layer during scribing
    39.
    发明申请
    Protective layer during scribing 有权
    划线时的保护层

    公开(公告)号：US20050070095A1

    公开(公告)日：2005-03-31

    申请号：US10676303

    申请日：2003-09-30

    申请人： Sujit Sharan ,  Thomas Debonis

    发明人： Sujit Sharan ,  Thomas Debonis

    IPC分类号： H01L21/301 ,  H01L21/304 ,  H01L21/78 ,  H05K3/00 ,  H05K3/28 ,  H01L21/4763

    CPC分类号： H05K3/0029 ,  H01L21/3043 ,  H01L21/78 ,  H05K3/0052 ,  H05K2201/10977 ,  H05K2203/0769 ,  H05K2203/1383

    摘要： A method including forming a chemically soluble coating on a plurality exposed contacts on a surface of a circuit substrate; scribing the surface of the substrate along scribe areas; and after scribing, removing a portion of the coating. A method including forming a circuit structure comprises a plurality of exposed contacts on a surface, a location of the exposed contacts defined by a plurality of scribe streets; forming a coating comprising a chemically soluble material on the exposed contacts; scribing the surface of the substrate along the scribe streets; and after scribing, removing the coating. A method including coating a surface of a circuit substrate comprising a plurality of exposed contacts with a chemically soluble material; scribing the surface of the substrate along scribe areas; removing the coating; and sawing the substrate in the scribe areas.

    摘要翻译： 一种方法，包括在电路基板的表面上的多个暴露的触点上形成化学上可溶的涂层; 沿着划线区域刻划基板的表面; 并且在划线之后，除去涂层的一部分。 包括形成电路结构的方法包括在表面上的多个暴露的触点，由多个划线条限定的暴露的触点的位置; 在暴露的触点上形成包含化学溶解材料的涂层; 沿着抄写街道刻划基板的表面; 并在划线后，去除涂层。 一种方法，包括用化学溶解的材料涂覆包括多个暴露的接触的电路基板的表面; 沿着划线区域刻划基板的表面; 去除涂层; 并在划片区域锯切基材。