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202 条记录 (耗时 0.051 秒)

    Data storage system
    31.
    发明申请
    Data storage system 失效

    公开(公告)号：US20060268608A1

    公开(公告)日：2006-11-30

    申请号：US11497325

    申请日：2006-08-02

    申请人： Mitsuhiro Noguchi ,  Akira Goda

    发明人： Mitsuhiro Noguchi ,  Akira Goda

    IPC分类号： G11C16/06

    CPC分类号： G06F11/1008 ,  G11C16/0483

    摘要： A data storage system, which includes a plurality of pages, each of which includes a plurality of first memory cells, from which at least binary data can be read-out a plurality of times without destruction; a circuit which receives data-output of at least one first page, detects an error in at least one bit of data, and outputs information of the error position; another circuit which determines whether data of an error bit is “1” or “0”. When the determination is “1” or “0”, the first memory cell of the first page is erased, and error-corrected data is written.

    Nonvolatile semiconductor memory device
    32.
    发明授权
    Nonvolatile semiconductor memory device 失效

    公开(公告)号：US07057936B2

    公开(公告)日：2006-06-06

    申请号：US10896081

    申请日：2004-07-22

    申请人： Toshitake Yaegashi ,  Akira Goda ,  Mitsuhiro Noguchi

    发明人： Toshitake Yaegashi ,  Akira Goda ,  Mitsuhiro Noguchi

    IPC分类号： G11C16/06

    CPC分类号： G11C16/0466 ,  G11C16/3468

    摘要： A cell array is configured by arranging a plurality of electrically writable erasable nonvolatile memory cells on a semiconductor substrate. Each of the memory cells has a charge accumulation layer formed via a first gate insulating film and a gate electrode formed on the charge accumulation layer via a second gate insulating film. A control circuit controls the sequence of writing and erasing the data into and from a memory cell selected in the memory cell. In writing the data into the memory cell, a first write operation is to apply a write pulse voltage with a first step-up voltage between the gate electrode and the semiconductor substrate. A second write operation is to apply a write pulse voltage with a second step-up voltage lower than the first step-up voltage.

    Semiconductor memory
    35.
    发明申请
    Semiconductor memory 有权

    公开(公告)号：US20050141291A1

    公开(公告)日：2005-06-30

    申请号：US11068228

    申请日：2005-03-01

    申请人： Mitsuhiro Noguchi ,  Akira Goda ,  Yasuhiko Matsunaga

    发明人： Mitsuhiro Noguchi ,  Akira Goda ,  Yasuhiko Matsunaga

    IPC分类号： G11C16/06 ,  G11C16/04 ,  G11C16/26 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

    CPC分类号： G11C16/26 ,  G11C16/0483 ,  H01L27/115

    摘要： A semiconductor memory including a memory cell unit, the memory cell unit comprising: a plurality of memory cells in which each conductance between current terminals changes according to held data, each having a plurality of current terminals connected in series between a first terminal and a second terminal, and each capable of electrically rewriting the data; a first select switching element electrically connecting said first terminal to a data transfer line; and a MISFET serving as a second select switching element connecting said second terminal to a reference potential line, wherein said semiconductor memory has a data read mode for forcing the first and second select switching elements of said memory cell unit into conduction, applying a read voltage for forcing a path between the current terminals into conduction or cut-off according to the data of a selected memory cell, to a control electrode of the selected memory cell, applying a pass voltage for forcing a path between the current terminals into conduction irrespectively of the data of each of the memory cells other than said selected memory cell, to the control electrode of each of the memory cells other than said selected memory cell, and detecting presence and absence or magnitude of a current between said data transfer line and said reference potential line, and in said data read mode, a conductance between current terminals of said MISFET is set lower than a conductance, in the case where the conductance between the current terminals is set to be the lowest, with regards to at least one of the memory cells other than said selected memory cell.

    Semiconductor memory device that is resistant to high voltages and a method of manufacturing the same
    39.
    发明授权
    Semiconductor memory device that is resistant to high voltages and a method of manufacturing the same 有权
    耐高电压的半导体存储器件及其制造方法

    公开(公告)号：US07919389B2

    公开(公告)日：2011-04-05

    申请号：US12498149

    申请日：2009-07-06

    申请人： Akira Goda ,  Mitsuhiro Noguchi

    发明人： Akira Goda ,  Mitsuhiro Noguchi

    IPC分类号： H01L21/76

    CPC分类号： H01L27/115 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573

    摘要： A semiconductor memory device having a memory cell region and a peripheral circuit region, and a method of manufacturing such a semiconductor memory device, are proposed, in which trench grooves are formed to be shallow in the memory cell region in order to improve the yield, and trench grooves are formed to be deep in the high voltage transistor region of the peripheral circuit region, in particular in a high voltage transistor region thereof, in order to improve the element isolation withstand voltage. A plurality of memory cell transistors having an ONO layer 15 serving as a charge accumulating insulating layer are provided in the memory cell region, where element isolation grooves 6 for these memory cell transistors are narrow and shallow. Two types of transistors, one for high voltage and the other for low voltage, having gate insulating layers 16 or 17, which are different from the ONO layer 15 in the memory cell region, are provided in the peripheral circuit region, where at least element isolation grooves 23 for high voltage transistors are wide and deep. In this way, it is possible to improve the degree of integration and yield in the memory cell region, and secure withstand voltage in the peripheral circuit region.

    摘要翻译： 提出了具有存储单元区域和外围电路区域的半导体存储器件以及制造这种半导体存储器件的方法，其中沟槽形成在存储单元区域中较浅以提高产量， 并且在周边电路区域的高电压晶体管区域，特别是在其高压晶体管区域中形成深沟槽，以便提高元件隔离耐受电压。 在存储单元区域中设置有多个具有作为电荷累积绝缘层的ONO层15的存储单元晶体管，其中用于这些存储单元晶体管的元件隔离槽6窄而浅。 在外围电路区域中设置两个类型的晶体管，一个用于高电压，另一个用于低电压，具有与存储单元区域中的ONO层15不同的栅极绝缘层16或17，其中至少元件 用于高压晶体管的隔离槽23宽而深。 以这种方式，可以提高存储单元区域的集成度和产量，并且确保外围电路区域中的耐受电压。

    Semiconductor memory
    40.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US07592666B2

    公开(公告)日：2009-09-22

    申请号：US10850408

    申请日：2004-05-21

    申请人： Mitsuhiro Noguchi ,  Akira Goda ,  Masayuki Tanaka

    发明人： Mitsuhiro Noguchi ,  Akira Goda ,  Masayuki Tanaka

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11568 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792

    摘要： A semiconductor memory having an electrically writable/erasable memory cell includes a first gate insulating layer made from a compound containing silicon and oxygen; a first charge-storage layer being in contact with the first gate insulating layer made from a silicon nitride film, a silicon oxynitride film, or an alumina film; a second insulating layer thicker than the first gate insulting layer; a second charge-storage layer being in contact with the second insulating layer; a third insulating layer thicker than the first gate insulating layer being in contact with the second charge-storage layer; and a control electrode upon the third insulating layer.

    摘要翻译： 具有电可写/可擦除存储单元的半导体存储器包括由含硅和氧的化合物制成的第一栅极绝缘层; 与由氮化硅膜，氮氧化硅膜或氧化铝膜构成的第一栅极绝缘层接触的第一电荷存储层; 比第一栅极绝缘层厚的第二绝缘层; 与第二绝缘层接触的第二电荷存储层; 比所述第一栅极绝缘层更厚的与所述第二电荷存储层接触的第三绝缘层; 以及在所述第三绝缘层上的控制电极。