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42 条记录 (耗时 0.029 秒)

    Method for producing a copper connection between two sides of a substrate
    32.
    发明授权
    Method for producing a copper connection between two sides of a substrate 有权
    在基板的两面之间制造铜连接的方法

    公开(公告)号：US08227340B2

    公开(公告)日：2012-07-24

    申请号：US12433033

    申请日：2009-04-30

    申请人： Uwe Seidel ,  Thorsten Obernhuber ,  Albert Birner ,  Georg Ehrentraut

    发明人： Uwe Seidel ,  Thorsten Obernhuber ,  Albert Birner ,  Georg Ehrentraut

    IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L21/461

    CPC分类号： H01L21/76898

    摘要： A method for producing an electrically conductive connection between a first surface of a semiconductor substrate and a second surface of the semiconductor substrate includes producing a hole, forming an electrically conductive layer that includes tungsten, removing the electrically conductive layer from the first surface of the semiconductor substrate, filling the hole with copper and thinning the semiconductor substrate. The hole is produced from the first surface of the semiconductor substrate into the semiconductor substrate. The electrically conductive layer is removed from the first surface of the semiconductor substrate, wherein the electrically conductive layer remains at least with reduced thickness in the hole. The semiconductor substrate is thinned starting from a surface, which is an opposite surface of the first surface of the semiconductor substrate, to obtain the second surface of the semiconductor substrate with the hole being uncovered at the second surface of the semiconductor substrate.

    摘要翻译： 一种用于在半导体衬底的第一表面和半导体衬底的第二表面之间制造导电连接的方法包括制造一个孔，形成包括钨的导电层，从半导体的第一表面去除导电层 衬底，用铜填充孔并使半导体衬底变薄。 该孔由半导体衬底的第一表面制成半导体衬底。 从半导体衬底的第一表面去除导电层，其中导电层在孔中至少具有减小的厚度。 半导体衬底从半导体衬底的第一表面的相对表面的表面开始变薄，以获得在半导体衬底的第二表面处未被覆盖的半导体衬底的第二表面。

    Method and Layout of Semiconductor Device with Reduced Parasitics
    33.
    发明申请
    Method and Layout of Semiconductor Device with Reduced Parasitics 有权
    具有减少寄生性的半导体器件的方法和布局

    公开(公告)号：US20110294273A1

    公开(公告)日：2011-12-01

    申请号：US13087102

    申请日：2011-04-14

    申请人： Albert Birner ,  Qiang Chen

    发明人： Albert Birner ,  Qiang Chen

    IPC分类号： H01L21/8234 ,  H01L21/336

    CPC分类号： H01L29/7835 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/7823

    摘要： An semiconductor device is disclosed. The device includes a semiconductor body, a layer of insulating material disposed over the semiconductor body, and a region of gate electrode material disposed over the layer of insulating material. Also included are a source region adjacent to gate region and a drain region adjacent to the gate region. A gate connection is disposed over the semiconductor body, wherein the gate connection includes a region of gate electrode material electrically coupling a contact region to the gate electrode. An insulating region is disposed on the semiconductor body beneath the gate connection.

    摘要翻译： 公开了一种半导体器件。 该器件包括半导体本体，设置在半导体本体上的绝缘材料层以及设置在绝缘材料层上的栅电极材料区域。 还包括与栅极区域相邻的源极区域和与栅极区域相邻的漏极区域。 栅极连接设置在半导体本体上，其中栅极连接包括将接触区域电耦合到栅电极的栅电极材料区域。 绝缘区域设置在栅极连接下方的半导体本体上。

    Method and layout of semiconductor device with reduced parasitics
    35.
    发明授权
    Method and layout of semiconductor device with reduced parasitics 有权
    减少寄生效应的半导体器件的方法和布局

    公开(公告)号：US08035140B2

    公开(公告)日：2011-10-11

    申请号：US11828944

    申请日：2007-07-26

    申请人： Albert Birner ,  Qiang Chen

    发明人： Albert Birner ,  Qiang Chen

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7835 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/7823

    摘要： An semiconductor device is disclosed. The device includes a semiconductor body, a layer of insulating material disposed over the semiconductor body, and a region of gate electrode material disposed over the layer of insulating material. Also included are a source region adjacent to gate region and a drain region adjacent to the gate region. A gate connection is disposed over the semiconductor body, wherein the gate connection includes a region of gate electrode material electrically coupling a contact region to the gate electrode. An insulating region is disposed on the semiconductor body beneath the gate connection.

    摘要翻译： 公开了一种半导体器件。 该器件包括半导体本体，设置在半导体本体上的绝缘材料层以及设置在绝缘材料层上的栅电极材料区域。 还包括与栅极区域相邻的源极区域和与栅极区域相邻的漏极区域。 栅极连接设置在半导体本体上，其中栅极连接包括将接触区域电耦合到栅电极的栅电极材料区域。 绝缘区域设置在栅极连接下方的半导体本体上。

    Fabrication method for fabricating a semiconductor structure and semiconductor structure
    40.
    发明申请
    Fabrication method for fabricating a semiconductor structure and semiconductor structure 审中-公开
    制造半导体结构和半导体结构的制造方法

    公开(公告)号：US20070037340A1

    公开(公告)日：2007-02-15

    申请号：US11477577

    申请日：2006-06-29

    申请人： Albert Birner ,  Andreas Weber ,  Rolf Weis

    发明人： Albert Birner ,  Andreas Weber ,  Rolf Weis

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/76224 ,  H01L27/10873 ,  H01L29/1037

    摘要： In a method for fabricating a semiconductor structure a semiconductor substrate comprising an active region with an uncovered top side is provided, at least one STI trench adjoining the active region is formed, and an STI divot is formed in the insulating filling. The at least one STI trench comprises an insulating filling extending to above the top side of the active region and the divot adjoins the active region and uncovers an edge of the uncovered top side of the active region. A hydrogen termination of the uncovered top side of the active region is formed and a heat treatment in a hydrogen atmosphere is carried out in order to form a rounding from the edge of the active region in such a way that the top side of the active region continuously merges into the STI divot.

    摘要翻译： 在制造半导体结构的方法中，提供包括具有未覆盖的顶侧的有源区的半导体衬底，形成与有源区邻接的至少一个STI沟槽，并且在绝缘填充物中形成STI纹。 所述至少一个STI沟槽包括延伸到有源区的顶侧上方的绝缘填充物，并且所述突起邻接所述有源区，并且露出所述有源区的未覆盖的顶侧的边缘。 形成有源区的未覆盖的顶侧的氢终端，并且在氢气氛中进行热处理，以便从有源区的边缘形成圆化，使得有源区的顶侧 不断融入STI纹章。