公开(公告)号：US20160358889A1

公开(公告)日：2016-12-08

申请号：US14730171

申请日：2015-06-03

Applicant: Apple Inc.

Inventor： Kwan-Yu Lai ,  Jun Zhai ,  Kunzhong Hu ,  Flynn P. Carson

IPC: H01L25/065 ,  H01L23/31 ,  H01L21/768 ,  H01L21/56 ,  H01L25/00 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L21/768 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106

Abstract: Packages including an embedded die with through silicon vias (TSVs) are described. In an embodiment, a first level die including TSVs is embedded between a first redistribution layer (RDL) and a second RDL, and a second level die is mounted on a top side of the first redistribution layer. In an embodiment, the first level die is an active die, less than 50 μm thick.

Abstract translation: 描述了包括通过硅通孔（TSV）的嵌入式裸片的封装。 在一个实施例中，包括TSV的第一级裸片被嵌入在第一重分配层（RDL）和第二RDL之间，并且第二级管芯安装在第一再分布层的顶侧。 在一个实施例中，第一级模具是小于50μm厚的有源管芯。

公开(公告)号：US20160013156A1

公开(公告)日：2016-01-14

申请号：US14541228

申请日：2014-11-14

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Kunzhong Hu ,  Chonghua Zhong

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/00

Abstract: In some embodiments, a semiconductor device package on package assembly may include a first package, a second package, and a third package. The first package may include a first surface, a second surface, a first die, and a first set of electrical conductors. The first set of electrical conductors may be configured to electrically connect the package on package assembly. The second package may include a third surface and a fourth surface, and a local memory module. The third surface may be coupled to the second surface. The first package may be electrically coupled to the second package. The third package may include a fifth surface and a sixth surface, and a main memory module. The fifth surface may be coupled to the fourth surface. The third package may be electrically coupled to the first package and/or the second package.

公开(公告)号：US20250157991A1

公开(公告)日：2025-05-15

申请号：US19023053

申请日：2025-01-15

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu ,  Vidhya Ramachandran

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/66 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/48 ,  H01L23/60 ,  H01L25/00

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

公开(公告)号：US12261132B2

公开(公告)日：2025-03-25

申请号：US18485709

申请日：2023-10-12

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Sanjay Dabral ,  SivaChandra Jangam ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/544 ,  H01L23/58

Abstract: Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.

公开(公告)号：US20250014960A1

公开(公告)日：2025-01-09

申请号：US18348934

申请日：2023-07-07

Applicant: Apple Inc.

Inventor： Jiongxin LU ,  Kunzhong Hu ,  Jun Zhai

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: Various embodiments of an integrated circuit (IC) die package are disclosed. An IC die package includes an IC die, an interposer structure electrically connected to the IC die, a first bonding structure, a second bonding structure, and a molding compound layer. The first bonding structure includes a first dielectric layer disposed on the IC die and a first conductive plug disposed in the first dielectric layer. The second bonding structure includes a second dielectric layer disposed on the interposer structure and a second conductive plug disposed in the second dielectric layer. The molding compound layer includes a mold region and a mold cavity.

公开(公告)号：US20240395686A1

公开(公告)日：2024-11-28

申请号：US18324612

申请日：2023-05-26

Applicant: Apple Inc.

Inventor： Wei Chen ,  Jie-Hua Zhao ,  Jun Zhai ,  Kunzhong Hu ,  Arun Sasi ,  Balaji Nandhivaram Muthuraman ,  Zezhou Liu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538

Abstract: Electronic packages and electronic systems are described in which a package redistribution layer of the electronic package includes structural features such a via line connections to reduce stress concentration, particularly when the package redistribution layer is formed of organic dielectric materials.

公开(公告)号：US12119304B2

公开(公告)日：2024-10-15

申请号：US17321080

申请日：2021-05-14

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Zhitao Cao ,  Kunzhong Hu

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/66 ,  H01L23/31 ,  H01L23/532 ,  H01L25/065

CPC classification number: H01L23/5384 ,  H01L21/56 ,  H01L22/12 ,  H01L23/31 ,  H01L23/53228 ,  H01L23/5386 ,  H01L25/0655

Abstract: Structures and methods of forming fine die-to-die interconnect routing are described. In an embodiment, a package includes a package-level RDL than spans across a die set and includes a plurality of die-to-die interconnects connecting contact pads between each die. In an embodiment, the plurality of die-to-die interconnects is embedded within one or more photoimageable organic dielectric layers.

公开(公告)号：US20240315054A1

公开(公告)日：2024-09-19

申请号：US18184527

申请日：2023-03-15

Applicant: Apple Inc.

Inventor： Jiongxin Lu ,  Kunzhong Hu

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065

CPC classification number: H10B80/00 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L21/561 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/73203 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/1436

Abstract: Electronic package and package on package (PoP) structures are described. The electronic package may be a top electronic package in a PoP structure. In an embodiment, the top electronic package includes back-to-face stacked dies and the top electronic package is inverted such that the stacked dies are between the top package substrate and an underlying package in a PoP structure. In an embodiment, the top electronic package includes face-to-back stacked dies such that the top die of the top electronic package is facing the underlying package in a PoP structure.

公开(公告)号：US11967528B2

公开(公告)日：2024-04-23

申请号：US18307554

申请日：2023-04-26

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Shawn Searles ,  Joseph T. DiBene, II ,  Mengzhi Pang

IPC: H01L21/77 ,  H01L21/66 ,  H01L23/00 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L21/77 ,  H01L22/20 ,  H01L24/32 ,  H01L24/73 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18 ,  H01L24/17 ,  H01L2224/12105 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/24195 ,  H01L2924/12 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104

Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

公开(公告)号：US20240105702A1

公开(公告)日：2024-03-28

申请号：US18178820

申请日：2023-03-06

Applicant: Apple Inc.

Inventor： Chonghua Zhong ,  Jiongxin Lu ,  Kunzhong Hu ,  Jun Zhai ,  Sanjay Dabral

IPC: H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/36 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/36 ,  H01L24/08 ,  H01L24/13 ,  H01L24/32 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/13082 ,  H01L2224/32245 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Semiconductor packages formed utilizing wafer reconstitution and optionally including an integrated heat spreader and methods of fabrication are described. In an embodiment, a semiconductor package includes a first package level, a second package level including one or more second-level chiplets, and a heat spreader bonded to the second package level with a metallic layer, which may include one or more intermetallic compounds formed by transient liquid phase bonding.