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    Stacked memory devices
    32.
    发明申请
    Stacked memory devices 有权
    堆叠式存储器件

    公开(公告)号：US20100246234A1

    公开(公告)日：2010-09-30

    申请号：US12654645

    申请日：2009-12-28

    申请人： Seung-eon Ahn ,  Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Hyun-ho Choi

    发明人： Seung-eon Ahn ,  Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Hyun-ho Choi

    IPC分类号： G11C5/02

    CPC分类号： G11C5/025 ,  G11C5/02 ,  G11C13/0023 ,  G11C2213/71 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/49 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-decoders electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups, and at least one pre-decoder electrically connected to the plurality of inter-decoders and disposed between the plurality of inter-decoders. A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-drivers electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups, and at least one pre-driver electrically connected to the plurality of inter-drivers, and disposed between the plurality of inter-drivers.

    摘要翻译： 层叠的存储器件可以包括衬底，堆叠在衬底上和衬底上并被分成多个组的多个存储器层，多个解码器电连接到多个存储器层并且布置在多个存储器层中的相应的一个 所述多个组以及至少一个预解码器电连接到所述多个解码器并且设置在所述多个解码器之间。 层叠的存储器件可以包括衬底，堆叠在衬底上和衬底上并被分成多个组的多个存储器层，多个驱动器电连接到多个存储器层并且被布置在多个存储器层中的相应的一个 所述多个组，以及电连接到所述多个驱动器之间的至少一个预驱动器，并且设置在所述多个驱动器之间。

    PHASE-CHANGE MEMORY DEVICE AND METHOD THAT MAINTAINS THE RESISTANCE OF A PHASE-CHANGE MATERIAL IN A SET STATE WITHIN A CONSTANT RESISTANCE RANGE
    34.
    发明申请
    PHASE-CHANGE MEMORY DEVICE AND METHOD THAT MAINTAINS THE RESISTANCE OF A PHASE-CHANGE MATERIAL IN A SET STATE WITHIN A CONSTANT RESISTANCE RANGE 有权
    相变存储器件和在恒定电阻范围内保持相变材料在电阻状态下的电阻的方法

    公开(公告)号：US20080013362A1

    公开(公告)日：2008-01-17

    申请号：US11772569

    申请日：2007-07-02

    申请人： Byung-gil Choi ,  Choong-keun Kwak ,  Sang-beom Kang ,  Joon-yong Choi

    发明人： Byung-gil Choi ,  Choong-keun Kwak ,  Sang-beom Kang ,  Joon-yong Choi

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C7/1006 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2211/5647

    摘要： Provided are a phase-change memory device and method that maintains a resistance of a phase-change material in a set state within a constant resistance range; In the method, data is provided to a first phase-change memory cell and then it is first determined whether data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are not identical, a complementary write current is provided to the first phase-change memory cell and it is second determined whether the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical; If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical, data is provided to a second phase-change memory cell;

    摘要翻译： 提供一种将相变材料的电阻维持在恒定电阻范围内的相变存储器件和方法， 在该方法中，将数据提供给第一相变存储器单元，然后首先确定存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据是否相同。 如果存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据不相同，则向第一相变存储单元提供互补写入电流，并且第二相位变换存储单元是否将数据 存储在第一相变存储单元中，提供给第一相变存储单元的数据相同; 如果存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据相同，则将数据提供给第二相变存储单元;

    Phase change random access memory (PRAM) device having variable drive voltages
    35.
    发明申请
    Phase change random access memory (PRAM) device having variable drive voltages 有权
    具有可变驱动电压的相变随机存取存储器（PRAM）装置

    公开(公告)号：US20070014150A1

    公开(公告)日：2007-01-18

    申请号：US11319601

    申请日：2005-12-29

    申请人： Woo-yeong Cho ,  Du-eung Kim ,  Sang-beom Kang ,  Choong-keun Kwak

    发明人： Woo-yeong Cho ,  Du-eung Kim ,  Sang-beom Kang ,  Choong-keun Kwak

    IPC分类号： G11C11/00 ,  G11C8/00

    CPC分类号： G11C13/0038 ,  G11C5/145 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/009

    摘要： A phase change memory device of one aspect includes a memory array including a plurality of phase change memory cells, a write boosting circuit, and a write driver. The write boosting circuit boosts a first voltage and outputs a first control voltage in response to a control signal in a first operation mode, and boosts the first voltage and outputs a second control voltage in response to the control signal in a second operation mode and a third operation mode. The write driver is driven by the first control voltage in the first operation mode and writes data to a selected memory cell of the memory array.

    摘要翻译： 一个方面的相变存储器件包括包括多个相变存储单元，写升压电路和写驱动器的存储器阵列。 写升压电路升压第一电压并响应于第一操作模式中的控制信号输出第一控制电压，并且在第二操作模式中响应于控制信号升高第一电压并输出第二控制电压，并且 第三操作模式。 写入驱动器由第一操作模式中的第一控制电压驱动，并将数据写入存储器阵列的所选存储单元。

    Semiconductor memory device and core layout thereof
    36.
    发明申请
    Semiconductor memory device and core layout thereof 失效
    半导体存储器件及其核心布局

    公开(公告)号：US20060215480A1

    公开(公告)日：2006-09-28

    申请号：US11316878

    申请日：2005-12-27

    申请人： Hye-jin Kim ,  Choong-keun Kwak ,  Woo-yeong Cho ,  Sang-beom Kang

    发明人： Hye-jin Kim ,  Choong-keun Kwak ,  Woo-yeong Cho ,  Sang-beom Kang

    IPC分类号： G11C8/00

    CPC分类号： G11C13/0028 ,  G11C13/0004

    摘要： A semiconductor memory device of one aspect includes a memory cell block including n global word lines, and corresponding m sub word lines for each of the n global word lines, where n and m are natural numbers. The memory device further includes a plurality of word line driving circuits which respectively control a voltage of the sub word lines according to a logic level of each corresponding global word line and inputted address signals, and a plurality of control circuits which transmit the address signals to the word line driving circuits or interrupt transmission of the address signals according to the logic level of the global word line. Each of the word line driving circuits includes a first transistor which maintains the voltage of the respective sub word line at a first voltage and a second transistor which maintains the voltage of the sub word line at the first voltage or a second voltage.

    摘要翻译： 一个方面的半导体存储器件包括包括n个全局字线的存储单元块，以及n个全局字线中的每一个的对应m个子字线，其中n和m是自然数。 存储装置还包括多个字线驱动电路，其分别根据每个对应的全局字线和输入的地址信号的逻辑电平分别控制子字线的电压，以及多个控制电路，其将地址信号发送到 字线驱动电路或根据全局字线的逻辑电平中断地址信号的传输。 每个字线驱动电路包括将相应子字线的电压维持在第一电压的第一晶体管和将子字线的电压维持在第一电压或第二电压的第二晶体管。

    Stacked memory devices
    38.
    发明授权
    Stacked memory devices 有权
    堆叠式存储器件

    公开(公告)号：US08611121B2

    公开(公告)日：2013-12-17

    申请号：US12662785

    申请日：2010-05-04

    申请人： Seung-eon Ahn ,  Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Hyun-ho Choi

    发明人： Seung-eon Ahn ,  Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Hyun-ho Choi

    IPC分类号： G11C5/02

    CPC分类号： G11C5/025 ,  G11C5/02 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C2213/71 ,  G11C2213/72

    摘要： A stacked memory device may include a substrate, a plurality of memory groups sequentially stacked on the substrate, each memory group including at least one memory layer, a plurality of X-decoder layers, at least one of the plurality of X-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups, and a plurality of Y-decoder layers disposed alternately with the plurality of X-decoder layers, at least one of the plurality of Y-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups.

    摘要翻译： 层叠的存储器件可以包括衬底，顺序地堆叠在衬底上的多个存储器组，每个存储器组包括至少一个存储器层，多个X译码器层，所述多个X译码器层中的至少一个是 设置在所述多个存储器组中的每个相邻的两个存储器组之间，以及与所述多个X解码器层交替布置的多个Y译码器层，所述多个Y译码器层中的至少一个设置在每个相邻的两个存储器组之间 的多个存储器组。

    Stacked memory device including a pre-decoder/pre-driver sandwiched between a plurality of inter-decoders/inter-drivers
    39.
    发明授权
    Stacked memory device including a pre-decoder/pre-driver sandwiched between a plurality of inter-decoders/inter-drivers 有权
    堆叠存储器件包括夹在多个解码器/驱动器之间的预解码器/预驱动器

    公开(公告)号：US08054665B2

    公开(公告)日：2011-11-08

    申请号：US12654645

    申请日：2009-12-28

    申请人： Seung-eon Ahn ,  Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Hyun-ho Choi

    发明人： Seung-eon Ahn ,  Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Hyun-ho Choi

    IPC分类号： G11C5/02

    CPC分类号： G11C5/025 ,  G11C5/02 ,  G11C13/0023 ,  G11C2213/71 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/49 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-decoders electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups, and at least one pre-decoder electrically connected to the plurality of inter-decoders and disposed between the plurality of inter-decoders. A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-drivers electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups, and at least one pre-driver electrically connected to the plurality of inter-drivers, and disposed between the plurality of inter-drivers.

    摘要翻译： 层叠的存储器件可以包括衬底，堆叠在衬底上和衬底上并被分成多个组的多个存储器层，多个解码器电连接到多个存储器层并且布置在多个存储器层中的相应的一个 所述多个组以及至少一个预解码器电连接到所述多个解码器并且设置在所述多个解码器之间。 层叠的存储器件可以包括衬底，堆叠在衬底上和衬底上并被分成多个组的多个存储器层，多个驱动器电连接到多个存储器层并且被布置在多个存储器层中的相应的一个 所述多个组，以及电连接到所述多个驱动器之间的至少一个预驱动器，并且设置在所述多个驱动器之间。

    Magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices
    40.
    发明申请
    Magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices 失效
    磁性分组存储器存储设备，包括这种设备的存储器系统以及控制这些设备的方法

    公开(公告)号：US20100208381A1

    公开(公告)日：2010-08-19

    申请号：US12658807

    申请日：2010-02-16

    申请人： Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Jong-wan Kim ,  Hyun-ho Choi ,  Young-pil Kim ,  Sung-chul Lee

    发明人： Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Jong-wan Kim ,  Hyun-ho Choi ,  Young-pil Kim ,  Sung-chul Lee

    IPC分类号： G11B19/02

    CPC分类号： G11C11/15 ,  G11C5/04

    摘要： A memory device is comprised of a magnetic structure that stores information in a plurality of domains of the magnetic structure. A write unit writes information to at least one of the plurality of domains of the magnetic structure by applying a write current to the magnetic structure in response to a control signal. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure in response to the control signal. A domain wall movement control unit is coupled to a portion of the magnetic structure and moves information stored in the plurality of domains in the magnetic structure to other domains in the magnetic structure in response to the control signal. The write unit, the read unit and the domain wall movement control unit are all coupled to the same control signal line that provides the control signal.

    摘要翻译： 存储器件由将磁信息存储在磁结构的多个域中的磁结构构成。 写单元响应于控制信号向磁结构施加写入电流，将信息写入磁结构的多个域中的至少一个。 读取单元通过响应于控制信号向磁性结构施加读取电流，从磁性结构的多个域中的至少一个域读取信息。 畴壁移动控制单元耦合到磁结构的一部分，并且响应于控制信号将存储在磁结构中的多个域中的信息移动到磁结构中的其他区域。 写单元，读单元和域壁移动控制单元都耦合到提供控制信号的相同控制信号线。