公开(公告)号：US07374993B2

公开(公告)日：2008-05-20

申请号：US10695959

申请日：2003-10-27

申请人： Matthew W. Miller ,  Cem Basceri

发明人： Matthew W. Miller ,  Cem Basceri

IPC分类号： H01L21/8242

CPC分类号： H01L27/1085 ,  H01L21/31155 ,  H01L21/31625 ,  H01L28/60

摘要： A method of forming a capacitor includes forming a first capacitor electrode over a semiconductor substrate. A capacitor dielectric region is formed onto the first capacitor electrode. The capacitor dielectric region has an exposed oxide containing surface. The exposed oxide containing surface of the capacitor dielectric region is treated with at least one of a borane or a silane. A second capacitor electrode is deposited over the treated oxide containing surface. The second capacitor electrode has an inner metal surface contacting against the treated oxide containing surface. Other aspects and implementations are contemplated.

公开(公告)号：US07358188B2

公开(公告)日：2008-04-15

申请号：US11362119

申请日：2006-02-23

申请人： Cem Basceri

发明人： Cem Basceri

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76823 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76895 ,  H01L21/76897

摘要： The invention includes methods of forming conductive metal silicides by reaction of metal with silicon. In one implementation, such a method includes providing a semiconductor substrate comprising an exposed elemental silicon containing surface. At least one of a nitride, boride, carbide, or oxide comprising layer is atomic layer deposited onto the exposed elemental silicon containing surface to a thickness no greater than 15 Angstroms. Such layer is exposed to plasma and a conductive reaction layer including at least one of an elemental metal or metal rich silicide is deposited onto the plasma exposed layer. Metal of the conductive reaction layer is reacted with elemental silicon of the substrate effective to form a conductive metal silicide comprising contact region electrically connecting the conductive reaction layer with the substrate. Other aspects and implementations are contemplated.

摘要翻译： 本发明包括通过金属与硅的反应形成导电金属硅化物的方法。 在一个实施方案中，这种方法包括提供包括暴露的含元素硅的表面的半导体衬底。 氮化物，硼化物，碳化物或氧化物层中的至少一种是原子层沉积到暴露的含元素硅表面上至不大于15埃的厚度。 这种层暴露于等离子体，并且包含元素金属或富金属硅化物中的至少一种的导电反应层沉积到等离子体暴露层上。 导电反应层的金属与衬底的元素硅反应，有效地形成导电金属硅化物，其包括将导电反应层与衬底电连接的接触区域。 考虑了其他方面和实现。

公开(公告)号：US20080083366A1

公开(公告)日：2008-04-10

申请号：US11854864

申请日：2007-09-13

申请人： Cem Basceri ,  Yuri Khlebnikov ,  Igor Khlebnikov ,  Cengiz Balkas ,  Murat Silan ,  Hudson Hobgood ,  Calvin Carter ,  Vijay Balakrishna ,  Robert Leonard ,  Adrian Powell ,  Valeri Tsvetkov ,  Jason Jenny

发明人： Cem Basceri ,  Yuri Khlebnikov ,  Igor Khlebnikov ,  Cengiz Balkas ,  Murat Silan ,  Hudson Hobgood ,  Calvin Carter ,  Vijay Balakrishna ,  Robert Leonard ,  Adrian Powell ,  Valeri Tsvetkov ,  Jason Jenny

IPC分类号： C30B23/00 ,  C30B25/00

CPC分类号： H01L29/1608 ,  C30B23/002 ,  C30B23/005 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/0254 ,  H01L21/02631 ,  H01L21/02634 ,  Y10T428/21

摘要： Micropipe-free, single crystal, silicon carbide (SiC) and related methods of manufacture are disclosed. The SiC is grown by placing a source material and seed material on a seed holder in a reaction crucible of the sublimation system, wherein constituent components of the sublimation system including the source material, reaction crucible, and seed holder are substantially free from unintentional impurities. By controlling growth temperature, growth pressure, SiC sublimation flux and composition, and a temperature gradient between the source material and the seed material or the SiC crystal growing on the seed material during the PVT process, micropipe-inducing process instabilities are eliminated and micropipe-free SiC crystal is grown on the seed material.

摘要翻译： 公开了无微波，单晶，碳化硅（SiC）和相关制造方法。 通过将源材料和种子材料放置在升华系统的反应坩埚中的种子保持器上来生长SiC，其中包括源材料，反应坩埚和种子保持器的升华系统的构成成分基本上没有无意的杂质。 通过控制PVT过程中生长温度，生长压力，SiC升华通量和组成以及种子材料或种子材料上生长的SiC晶体之间的温度梯度，消除了微管诱导过程的不稳定性， 在种子材料上生长游离的SiC晶体。

公开(公告)号：US07344755B2

公开(公告)日：2008-03-18

申请号：US10646673

申请日：2003-08-21

申请人： Kevin L. Beaman ,  Ronald A. Weimer ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Trung T. Doan ,  Cem Basceri ,  David J. Kubista ,  Lingyi A. Zheng

发明人： Kevin L. Beaman ,  Ronald A. Weimer ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Trung T. Doan ,  Cem Basceri ,  David J. Kubista ,  Lingyi A. Zheng

IPC分类号： C23C16/00

CPC分类号： C23C16/45546 ,  C23C16/4404

摘要： The present disclosure provides methods and apparatus that may be used to process microfeature workpieces, e.g., semiconductor wafers. Some aspects have particular utility in depositing TiN in a batch process. One implementation involves pretreating a surface of a process chamber by contemporaneously introducing first and second pretreatment precursors (e.g., TiCl4 and NH3) to deposit a pretreatment material on a the chamber surface. After the pretreatment, the first microfeature workpiece may be placed in the chamber and TiN may be deposited on the microfeature workpiece by alternately introducing quantities of first and second deposition precursors.

摘要翻译： 本公开提供了可用于处理微特征工件（例如半导体晶片）的方法和装置。 一些方面在分批过程中沉积TiN具有特殊的用途。 一个实施方案包括通过同时引入第一和第二预处理前体（例如，TiCl 4和NH 3）来预处理处理室的表面，以将预处理材料沉积在室表面上 。 在预处理之后，可以将第一微特征工件放置在腔室中，并且可以通过交替地引入量的第一和第二沉积前体将TiN沉积在微特征工件上。

公开(公告)号：US07253076B1

公开(公告)日：2007-08-07

申请号：US09590795

申请日：2000-06-08

申请人： Vishnu K. Agarwal ,  Garo Derderian ,  Gurtej S. Sandhu ,  Weimin M. Li ,  Mark Visokay ,  Cem Basceri ,  Sam Yang

发明人： Vishnu K. Agarwal ,  Garo Derderian ,  Gurtej S. Sandhu ,  Weimin M. Li ,  Mark Visokay ,  Cem Basceri ,  Sam Yang

IPC分类号： H01L21/20

CPC分类号： H01L28/84 ,  H01L21/31637 ,  H01L28/55 ,  H01L28/65

摘要： Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient. A nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the processing or afterwards to passivate the ruthenium for improved compatibility with high-dielectric-constant dielectric materials. Processing in an oxidizing ambient may also be performed to passivate the roughened layer. The roughened layer of ruthenium may be used to form an enhanced-surface-area electrically conductive layer. The resulting enhanced-surface-area electrically conductive layer may form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like. In another approach, a tungsten nitride layer is provided as an first electrode of such a capacitor. The capacitor, or at least the tungsten nitride layer, is annealed to increase the capacitance of the capacitor.

摘要翻译： 具有增加的电容的电容器包括增强的表面积（粗糙表面）导电层或与高介电常数材料相容的其它层。 在一种方法中，用于这种电容器的增强表面积导电层是通过在高温或高于500℃，低压75托或更低，最理想的5托或更低的高温下处理氧化钌层形成的， 产生具有至少约100埃的平均特征尺寸的纹理表面的粗糙钌层。 初始氧化钌层可以通过化学气相沉积技术或溅射技术等来提供。 该层可以形成在下面的导电层上。 处理可以在惰性环境或还原环境中进行。 可以在处理期间或之后使用供氮环境或供氮还原环境以钝化钌以改善与高介电常数电介质材料的相容性。 氧化环境中的处理也可以进行以钝化粗糙层。 可以使用粗糙化的钌层来形成增强表面积的导电层。 所形成的增强表面积导电层可以在诸如DRAM等的存储单元中的集成电路中形成存储电容器的板。 在另一种方法中，提供氮化钨层作为这种电容器的第一电极。 电容器或至少氮化钨层被退火以增加电容器的电容。

公开(公告)号：US07235138B2

公开(公告)日：2007-06-26

申请号：US10646607

申请日：2003-08-21

申请人： Lingyi A. Zheng ,  Trung T. Doan ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Ronald A. Weimer ,  David J. Kubista ,  Kevin L. Beaman ,  Cem Basceri

发明人： Lingyi A. Zheng ,  Trung T. Doan ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Ronald A. Weimer ,  David J. Kubista ,  Kevin L. Beaman ,  Cem Basceri

IPC分类号： C23C16/00 ,  H01L21/306 ,  C23F1/00

CPC分类号： C23C16/4583 ,  C23C16/45546 ,  C23C16/45578 ,  Y10S206/832

摘要： The present disclosure describes apparatus and methods for processing microfeature workpieces, e.g., by depositing material on a microelectronic semiconductor using atomic layer deposition. Some of these apparatus include microfeature workpiece holders that include gas distributors. One exemplary implementation provides a microfeature workpiece holder adapted to hold a plurality of microfeature workpieces. This workpiece holder includes a plurality of workpiece supports and a gas distributor. The workpiece supports are adapted to support a plurality of microfeature workpieces in a spaced-apart relationship to define a process space adjacent a surface of each microfeature workpiece. The gas distributor includes an inlet and a plurality of outlets, with each of the outlets positioned to direct a flow of process gas into one of the process spaces.

摘要翻译： 本公开描述了用于处理微特征工件的装置和方法，例如通过使用原子层沉积在微电子半导体上沉积材料。 这些设备中的一些包括微型工件保持器，其包括气体分配器。 一个示例性实施例提供了适于保持多个微特征工件的微特征工件保持器。 该工件保持器包括多个工件支撑件和气体分配器。 工件支撑件适于以间隔的关系支撑多个微特征工件以限定与每个微特征工件的表面相邻的工艺空间。 气体分配器包括入口和多个出口，其中每个出口被定位成将处理气体流引导到处理空间中的一个中。

公开(公告)号：US20070093034A1

公开(公告)日：2007-04-26

申请号：US11606478

申请日：2006-11-29

申请人： Cem Basceri ,  Garo Derderian

发明人： Cem Basceri ,  Garo Derderian

IPC分类号： H01L21/20

CPC分类号： H01L21/7687 ,  H01L21/76877 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/75 ,  Y10S438/964

摘要： The invention includes a method of forming a semiconductor construction. A semiconductor substrate is provided, and a conductive node is formed to be supported by the semiconductor substrate. A first conductive material is formed over the conductive node and shaped as a container. The container has an opening extending therein and an upper surface proximate the opening. The container opening is at least partially filled with an insulative material. A second conductive material is formed over the at least partially filled container opening and physically against the upper surface of the container. The invention also includes semiconductor structures.

摘要翻译： 本发明包括形成半导体结构的方法。 提供半导体衬底，并且形成由半导体衬底支撑的导电节点。 第一导电材料形成在导电节点上并成形为容器。 容器具有在其中延伸的开口和靠近开口的上表面。 容器开口至少部分地填充有绝缘材料。 第二导电材料形成在至少部分填充的容器开口上并且物理地抵靠容器的上表面。 本发明还包括半导体结构。

公开(公告)号：US20070093022A1

公开(公告)日：2007-04-26

申请号：US11638931

申请日：2006-12-13

申请人： Cem Basceri ,  Gurtej Sandhu

发明人： Cem Basceri ,  Gurtej Sandhu

IPC分类号： H01L21/8242 ,  H01L51/40

CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852

摘要： A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes comprising sidewalls. The plurality of capacitor electrodes are supported at least in part with a retaining structure which engages the sidewalls, with the retaining structure comprising a fluid pervious material. A capacitor dielectric material is deposited over the capacitor electrodes through the fluid pervious material of the retaining structure effective to deposit capacitor dielectric material over portions of the sidewalls received below the retaining structure. Capacitor electrode material is deposited over the capacitor dielectric material through the fluid pervious material of the retaining structure effective to deposit capacitor electrode material over at least some of the capacitor dielectric material received below the retaining structure. Integrated circuitry independent of method of fabrication is also contemplated.

摘要翻译： 形成多个电容器的方法包括提供包括侧壁的多个电容器电极。 多个电容器电极至少部分地由与侧壁接合的保持结构支撑，保持结构包括透液材料。 电容器电介质材料沉积在电容器电极上，通过保持结构的流体可渗透材料，其有效地将电容器电介质材料沉积在容纳在保持结构下方的侧壁的部分上。 电容器电极材料通过保持结构的流体可透过材料沉积在电容器介电材料上，有效地将电容器电极材料沉积在容纳在保持结构下方的电容器电介质材料的至少一些之上。 还考虑了与制造方法无关的集成电路。

公开(公告)号：US07192828B2

公开(公告)日：2007-03-20

申请号：US10819420

申请日：2004-04-07

申请人： Cem Basceri ,  Gurtej S. Sandhu ,  Sam Yang

发明人： Cem Basceri ,  Gurtej S. Sandhu ,  Sam Yang

IPC分类号： H01L21/8242

CPC分类号： H01L28/75 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02197 ,  H01L21/02271 ,  H01L21/31604 ,  H01L21/31683 ,  H01L27/10811 ,  H01L28/55

摘要： A stabilized capacitor using non-oxide electrodes and high dielectric constant oxide dielectric materials and methods of making such capacitors and their incorporation into DRAM cells is provided. A preferred method includes providing a non-oxide electrode, oxidizing an upper surface of the non-oxide electrode, depositing a high dielectric constant oxide dielectric material on the oxidized surface of the non-oxide electrode, and depositing an upper layer electrode on the high dielectric constant oxide dielectric material.

摘要翻译： 提供了使用非氧化物电极和高介电常数氧化物电介质材料的稳定电容器以及制造这种电容器并将其并入DRAM单元的方法。 优选的方法包括提供非氧化物电极，氧化非氧化物电极的上表面，在非氧化物电极的氧化表面上沉积高介电常数氧化物电介质材料，以及在高电极上沉积上层电极 介电常数氧化物介电材料。

公开(公告)号：US20070026601A1

公开(公告)日：2007-02-01

申请号：US11517209

申请日：2006-09-06

申请人： Cem Basceri ,  F. Gealy ,  Gurtej Sandhu

发明人： Cem Basceri ,  F. Gealy ,  Gurtej Sandhu

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L27/10855 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/57

摘要： The invention includes methods in which metal oxide dielectric materials are deposited over barrier layers. The barrier layers can comprise compositions of metal and one or more of carbon, boron and nitrogen, and the metal oxide of the dielectric material can comprise the same metal as the barrier layer. The dielectric material/barrier layer constructions can be incorporated into capacitors. The capacitors can be used in, for example, DRAM cells, which in turn can be used in electronic systems.

摘要翻译： 本发明包括其中金属氧化物电介质材料沉积在阻挡层上的方法。 阻挡层可以包括金属和碳，硼和氮中的一种或多种的组合物，并且介电材料的金属氧化物可以包含与阻挡层相同的金属。 电介质材料/阻挡层结构可以结合到电容器中。 电容器可以用在例如DRAM单元中，DRAM单元又可以用在电子系统中。