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    Metal seed layer deposition
    36.
    发明授权
    Metal seed layer deposition 有权
    金属种子层沉积

    公开(公告)号：US07879716B2

    公开(公告)日：2011-02-01

    申请号：US11687017

    申请日：2007-03-16

    申请人： Steven P. Barkyoumb ,  Jonathan D. Chapple-Sokol ,  Edward C. Cooney, III ,  Keith E. Downes ,  Thomas L. McDevitt ,  William J. Murphy

    发明人： Steven P. Barkyoumb ,  Jonathan D. Chapple-Sokol ,  Edward C. Cooney, III ,  Keith E. Downes ,  Thomas L. McDevitt ,  William J. Murphy

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76843 ,  H01L21/76856 ,  H01L21/76859 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76871 ,  H01L21/76873

    摘要： A method and structure for reducing the corrosion of the copper seed layer during the fabrication process of a semiconductor structure. Before the structure (or the wafer containing the structure) exits the vacuum environment of the sputter tool, the structure is warmed up to a temperature above the water condensation temperature of the environment outside the sputter tool. As a result, water vapor would not condense on the structure when the structure exits the sputter tool, and therefore, corrosion of the seed layer by the water vapor is prevented. Alternatively, a protective layer resistant to water vapor can be formed on top of the seed layer before the structure exits the sputter tool environment. In yet another alternative embodiment, the seed layer can comprises a copper alloy (such as with aluminum) which grows a protective layer resistant to water vapor upon exposure to water vapor.

    摘要翻译： 一种用于在半导体结构的制造过程中减少铜籽晶层的腐蚀的方法和结构。 在结构（或包含结构的晶片）离开溅射工具的真空环境之前，将结构加热到高于溅射工具外部环境的水冷凝温度的温度。 结果，当结构离开溅射工具时，水蒸气不会在结构上冷凝，因此防止了水蒸气对种子层的腐蚀。 或者，在结构离开溅射工具环境之前，可以在籽晶层的顶部形成耐水蒸汽的保护层。 在另一替代实施例中，种子层可以包括铜合金（例如用铝），其在暴露于水蒸汽时生长出耐水蒸气的保护层。

    Stress-modified device structures, methods of fabricating such stress-modified device structures, and design structures for an integrated circuit
    37.
    发明授权
    Stress-modified device structures, methods of fabricating such stress-modified device structures, and design structures for an integrated circuit 有权
    应力改进的器件结构，制造这种应力改进的器件结构的方法以及集成电路的设计结构

    公开(公告)号：US07843039B2

    公开(公告)日：2010-11-30

    申请号：US12030917

    申请日：2008-02-14

    申请人： Edward C. Cooney, III ,  Mark Dupuis ,  William J. Murphy ,  Steven S. Williams

    发明人： Edward C. Cooney, III ,  Mark Dupuis ,  William J. Murphy ,  Steven S. Williams

    IPC分类号： H01L29/73 ,  H01L21/331

    CPC分类号： H01L29/732 ,  H01L21/76224 ,  H01L21/76843 ,  H01L21/8222 ,  H01L21/8228 ,  H01L27/0825 ,  H01L27/0826 ,  H01L29/0649 ,  H01L29/456

    摘要： Stress-modified device structures, methods of fabricating such stress-modified device structures, and design structures for an integrated circuit. An electrical characteristic of semiconductor devices formed on a common substrate, such as the current gains of bipolar junction transistors, may be altered by modifying stresses in structures indirectly on or over, or otherwise indirectly coupled with, the semiconductor devices. The structures, which may be liners for contacts in a contact level of an interconnect, are physically spaced away from, and not in direct physical contact with, the respective semiconductor devices because at least one additional intervening material or structure is situated between the stress-imparting structures and the stress-modified devices. The intervening materials or structures, such as contacts extending through an insulating layer of a local interconnect level between the contact level and the semiconductor devices, provide paths for the transfer of stress from the stress-imparting structures to the stress-modified semiconductor devices.

    摘要翻译： 应力改进的器件结构，制造这种应力改进的器件结构的方法以及集成电路的设计结构。 形成在公共衬底上的半导体器件的电特性，例如双极结晶体管的电流增益，可以通过间接地或间接地与半导体器件耦合的结构中的应力来改变。 在互连的接触电平中可以为触点的衬垫的结构物理上与相应的半导体器件隔开距离并且不与其直接物理接触，因为至少一个附加的介入材料或结构位于应力 - 赋予结构和应力改进的装置。 中间的材料或结构，例如延伸穿过接触层和半导体器件之间的局部互连层的绝缘层的触点，提供了将应力从应力赋予结构转移到应力改性半导体器件的路径。

    OPTIMAL TUNGSTEN THROUGH WAFER VIA AND PROCESS OF FABRICATING SAME
    38.
    发明申请
    OPTIMAL TUNGSTEN THROUGH WAFER VIA AND PROCESS OF FABRICATING SAME 失效
    通过WAFER的最佳方式和制作方法

    公开(公告)号：US20090280643A1

    公开(公告)日：2009-11-12

    申请号：US12115568

    申请日：2008-05-06

    申请人： Paul S. Andry ,  Edward C. Cooney, III ,  Peter J. Lindgren ,  Dorreen J. Ossenkop ,  Cornelia K. Tsang

    发明人： Paul S. Andry ,  Edward C. Cooney, III ,  Peter J. Lindgren ,  Dorreen J. Ossenkop ,  Cornelia K. Tsang

    IPC分类号： H01L23/482 ,  H01L21/768 ,  H01L21/44 ,  H01L23/48 ,  H01L29/40 ,  H01L23/52

    CPC分类号： H01L23/485 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of optimally filling a through via within a through wafer via structure with a conductive metal such as, for example, W is provided. The inventive method includes providing a structure including a substrate having at least one aperture at least partially formed through the substrate. The at least one aperture of the structure has an aspect ratio of at least 20:1 or greater. Next, a refractory metal-containing liner such as, for example, Ti/TiN, is formed on bare sidewalls of the substrate within the at least one aperture. A conductive metal seed layer is then formed on the refractory metal-containing liner. In the invention, the conductive metal seed layer formed is enriched with silicon and has a grain size of about 5 nm or less. Next, a conductive metal nucleation layer is formed on the conductive metal seed layer. The conductive metal nucleation layer is also enriched with silicon and has a grain size of about 20 nm or greater. Next, a conductive metal is formed on the conductive metal nucleation layer. After performing the above processing steps, a backside planarization process is performed to convert the at least one aperture into at least one through via that is now optimally filled with a conductive metal.

    摘要翻译： 提供了一种在具有例如W的导电金属的直通晶片通孔结构内最佳地填充通孔的方法。 本发明的方法包括提供一种结构，其包括具有至少一个通过该基底部分形成的孔的基底。 该结构的至少一个孔具有至少20:1或更大的纵横比。 接下来，在至少一个孔内的衬底的裸露的侧壁上形成诸如Ti / TiN的含难熔金属衬里。 然后在含难熔金属的衬垫上形成导电金属种子层。 在本发明中，所形成的导电金属晶种层富含硅，其晶粒尺寸为约5nm或更小。 接着，在导电性金属种子层上形成导电性金属成核层。 导电金属成核层也富含硅，其粒径约为20nm或更大。 接着，在导电性金属成核层上形成导电性金属。 在执行上述处理步骤之后，执行背面平面化处理以将至少一个孔转换成现在被最佳地填充有导电金属的至少一个通孔。

    Process to create robust contacts and interconnects
    39.
    发明授权
    Process to create robust contacts and interconnects 失效
    创建稳健的联系人和互连的过程

    公开(公告)号：US06534394B1

    公开(公告)日：2003-03-18

    申请号：US09660711

    申请日：2000-09-13

    申请人： Edward C. Cooney, III ,  William J. Murphy

    发明人： Edward C. Cooney, III ,  William J. Murphy

    IPC分类号： H01L214763

    CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865

    摘要： A method is provided to preferably create robust contacts and interconnects by depositing a thin layer of a first conductive material on a wafer through a non-ionized deposition process. The thin layer overlays the wafer and lines any apertures in the wafer. Deposition of a first conductive material is followed by depositing another thin layer of a second conductive material by an ionized deposition process. In this manner, the second conductive material overlays the first conductive material and additionally lines the wafer and any apertures in the wafer. Furthermore, if the apertures open to underlying areas, the conductive materials that line the apertures preferably create a conductive film that can form a plurality of contacts between the conductive film and the underlying areas.

    摘要翻译： 通过非电离沉积工艺在晶片上沉积第一导电材料的薄层来提供一种方法来优选地产生坚固的触点和互连。 薄层覆盖晶片并且对晶片中的任何孔进行排列。 第一导电材料的沉积之后是通过电离沉积工艺沉积另一薄层的第二导电材料。 以这种方式，第二导电材料覆盖第一导电材料，并且另外导引晶片和晶片中的任何孔。 此外，如果孔向下面的区域打开，则线孔的导电材料优选地形成导电膜，该导电膜可以在导电膜和下面的区域之间形成多个接触。