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1.发明授权Fluorine barrier layer between conductor and insulator for degradation prevention 有权导体和绝缘体之间的氟阻隔层用于防止降解公开(公告)号：US06214730B1
公开(公告)日：2001-04-10
申请号：US09257372
申请日：1999-02-25
IPC分类号： H01L2144
CPC分类号： H01L21/28568 , H01L21/76801 , H01L21/76814 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L21/76838 , Y10S438/963
摘要： Method of improving the resistance of a metal against degradation from exposure to fluorine released from a fluorine-containing material by forming a fluorine-barrier layer between the insulator material and the metal. The invention is especially useful in improving corrosion and poisoning resistance of metallurgy, such as aluminum metallurgy, in semiconductor structures. The invention also covers integrated circuit structures made by this method.
摘要翻译： 通过在绝缘体材料和金属之间形成氟阻隔层，提高金属抵抗从暴露于含氟材料的氟降解的方法。 本发明特别可用于改善半导体结构中的冶金冶金等的耐腐蚀和耐中毒性。 本发明还涉及通过该方法制成的集成电路结构。
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2.发明授权Fluorine barrier layer between conductor and insulator for degradation prevention 失效导体和绝缘体之间的氟阻隔层用于防止降解
公开(公告)号：US5930655A
公开(公告)日：1999-07-27
申请号：US937622
申请日：1997-09-25
IPC分类号： H01L21/285 , H01L21/314 , H01L21/316 , H01L21/768 , H01L23/522 , H01L21/322
CPC分类号： H01L21/28568 , H01L21/76801 , H01L21/76814 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L21/76838 , Y10S438/963
摘要： Method of improving the resistance of a metal against degradation from exposure to fluorine released from a fluorine-containing material by forming a fluorine-barrier layer between the insulator material and the metal. The invention is especially useful in improving corrosion and poisoning resistance of metallurgy, such as aluminum metallurgy, in semiconductor structures. The invention also covers integrated circuit structures made by this method.
摘要翻译： 通过在绝缘体材料和金属之间形成氟阻隔层，提高金属抵抗从暴露于含氟材料的氟降解的方法。 本发明特别可用于改善半导体结构中的冶金冶金等的耐腐蚀和耐中毒性。 本发明还涉及通过该方法制成的集成电路结构。
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3.发明授权Fluorine-free barrier layer between conductor and insulator for degradation prevention 失效导体和绝缘体之间的无氟阻隔层，用于防止降解公开(公告)号：US06310300B1
公开(公告)日：2001-10-30
申请号：US08744846
申请日：1996-11-08
IPC分类号： H05K100
CPC分类号： H01L21/28568 , H01L21/76801 , H01L21/76814 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L21/76838 , Y10S438/963
摘要： Integrated circuit structure having improved resistance in metal against degradation from exposure to fluorine released from a fluorine-containing material by forming a fluorine barrier layer between the insulator material and the metal. The invention is especially useful in improving corrosion and poisoning resistance of metallurgy, such as aluminum metallurgy, in semiconductor structures.
摘要翻译： 集成电路结构，通过在绝缘体材料和金属之间形成氟阻隔层，具有改进的金属电阻，防止从暴露于含氟材料释放的氟的劣化。 本发明特别可用于改善半导体结构中的冶金冶金等的耐腐蚀和耐中毒性。
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4.发明授权Method for providing fluorine barrier layer between conductor and insulator for degradation prevention 失效在导体和绝缘体之间提供氟阻隔层以防止劣化的方法
公开(公告)号：US6066577A
公开(公告)日：2000-05-23
申请号：US937367
申请日：1997-09-25
IPC分类号： H01L21/285 , H01L21/314 , H01L21/316 , H01L21/768 , H01L23/522 , H01L21/31 , H01L21/469
CPC分类号： H01L21/28568 , H01L21/76801 , H01L21/76814 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L21/76838 , Y10S438/963
摘要： Method of improving the resistance of a metal against degradation from exposure to fluorine released from a fluorine-containing material by forming a fluorine-free silicon dioxide barrier layer between the insulator material and the metal. The invention is especially useful in improving corrosion and poisoning resistance of metallurgy, such as aluminum metallurgy, in semiconductor structures. The invention also covers integrated circuit structures made by this method.
摘要翻译： 通过在绝缘体材料和金属之间形成无氟二氧化硅阻挡层来提高金属抵抗从暴露于氟的氟降低的方法。 本发明特别可用于改善半导体结构中的冶金冶金等的耐腐蚀和耐中毒性。 本发明还涉及通过该方法制成的集成电路结构。
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公开(公告)号：US07015150B2
公开(公告)日：2006-03-21
申请号：US10709747
申请日：2004-05-26
申请人： Edward C. Cooney, III , John A. Fitzsimmons , Jeffrey P. Gambino , Stephen E. Luce , Thomas L. McDevitt , Lee M. Nicholson , Anthony K. Stamper
发明人： Edward C. Cooney, III , John A. Fitzsimmons , Jeffrey P. Gambino , Stephen E. Luce , Thomas L. McDevitt , Lee M. Nicholson , Anthony K. Stamper
IPC分类号： H01L21/31 , H01L21/302
CPC分类号： H01L21/76831 , H01L21/02107 , H01L21/02203 , H01L21/02337 , H01L21/0234 , H01L21/02362 , H01L21/3105 , H01L21/31116 , H01L21/31695 , H01L21/76802 , H01L21/76807 , H01L21/76826 , H01L21/76843 , H01L21/76844 , H01L21/76868
摘要： Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant is absorbed or retained in exposed pores in the patterned dielectric layer and then a second reactant is introduced into openings such that it enters the exposed pores, while first reactant molecules are simultaneously being outgassed. The second reactant reacts in-situ with the outgassed first reactant molecules at a mouth region of the exposed pores to form the pore-closing layer across the mouth region of exposed pores, while retaining a portion of each pore's porosity to maintain characteristics and properties of the porous low-k dielectric layer. Optionally, the first reactant may be adsorbed onto the low-k dielectric such that upon introduction of the second reactant into the patterned dielectric openings, a reactive liner is also formed on the low-k dielectric.
摘要翻译： 具有闭孔层的方法和结构，用于封闭图案化的多孔低k电介质层中的暴露孔，以及可选地在低k电介质上的反应性衬垫。 第一反应物被吸收或保留在图案化介电层中的暴露孔中，然后将第二反应物引入开口中，使得其进入暴露的孔，同时第一反应物分子同时脱气。 第二反应物与暴露孔的口部区域处的脱气的第一反应物分子原位反应，以形成穿过暴露孔的口部区域的孔闭合层，同时保留每个孔隙的一部分以保持其孔的特性和性质 多孔低k电介质层。 任选地，第一反应物可以被吸附到低k电介质上，使得当将第二反应物引入图案化的电介质开口中时，还在低k电介质上形成反应性衬垫。
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6.发明申请VERTICAL INTEGRATED CIRCUIT SWITCHES, DESIGN STRUCTURE AND METHODS OF FABRICATING SAME 有权垂直集成电路开关，设计结构及其制作方法公开(公告)号：US20100263998A1
公开(公告)日：2010-10-21
申请号：US12426561
申请日：2009-04-20
IPC分类号： H01H59/00 , H01L21/50 , G06F17/50 , H01L21/3213
CPC分类号： H01H59/0009 , H01L2924/0002 , H01L2924/00
摘要： Vertical integrated MEMS switches, design structures and methods of fabricating such vertical switches is provided herein. The method of manufacturing a MEMS switch, includes forming at least two vertically extending vias in a wafer and filling the at least two vertically extending vias with a metal to form at least two vertically extending wires. The method further includes opening a void in the wafer from a bottom side such that at least one of the vertically extending wires is moveable within the void.
摘要翻译： 本文提供垂直集成MEMS开关，制造这种垂直开关的设计结构和方法。 制造MEMS开关的方法包括在晶片中形成至少两个垂直延伸的通孔，并用金属填充至少两个垂直延伸的通孔以形成至少两个垂直延伸的导线。 该方法还包括从底侧打开晶片中的空隙，使得垂直延伸的线中的至少一个可在空隙内移动。
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7.发明授权Vertical integrated circuit switches, design structure and methods of fabricating same 有权垂直集成电路开关，设计结构及其制造方法公开(公告)号：US08604898B2
公开(公告)日：2013-12-10
申请号：US12426561
申请日：2009-04-20
IPC分类号： H01H51/22
CPC分类号： H01H59/0009 , H01L2924/0002 , H01L2924/00
摘要： Vertical integrated MEMS switches, design structures and methods of fabricating such vertical switches is provided herein. The method of manufacturing a MEMS switch, includes forming at least two vertically extending vias in a wafer and filling the at least two vertically extending vias with a metal to form at least two vertically extending wires. The method further includes opening a void in the wafer from a bottom side such that at least one of the vertically extending wires is moveable within the void.
摘要翻译： 本文提供垂直集成MEMS开关，制造这种垂直开关的设计结构和方法。 制造MEMS开关的方法包括在晶片中形成至少两个垂直延伸的通孔，并用金属填充至少两个垂直延伸的通孔以形成至少两个垂直延伸的导线。 该方法还包括从底侧打开晶片中的空隙，使得垂直延伸的线中的至少一个可在空隙内移动。
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8.发明授权Device and methodology for reducing effective dielectric constant in semiconductor devices 有权用于降低半导体器件中有效介电常数的器件和方法公开(公告)号：US08343868B2
公开(公告)日：2013-01-01
申请号：US13005201
申请日：2011-01-12
申请人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
发明人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
IPC分类号： H01L21/00
CPC分类号： B82Y30/00 , H01L21/0332 , H01L21/31111 , H01L21/31144 , H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.
摘要翻译： 一种制造结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成次光刻 特征跨越到多个互连的侧壁。
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公开(公告)号：US20120193790A1
公开(公告)日：2012-08-02
申请号：US13444193
申请日：2012-04-11
申请人： Paul S. Andry , Edward C. Cooney, III , Edmund J. Sprogis , Anthony K. Stamper , Cornelia K. Tsang
发明人： Paul S. Andry , Edward C. Cooney, III , Edmund J. Sprogis , Anthony K. Stamper , Cornelia K. Tsang
IPC分类号： H01L23/498
CPC分类号： H01L24/10 , H01L23/5384 , H01L24/13 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/05684 , H01L2224/05686 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01327 , H01L2924/04953 , H01L2924/12044 , H01L2924/15311 , H01L2924/00 , H01L2924/00014 , H01L2924/049
摘要： A back of a dielectric transparent handle substrate is coated with a blanket conductive film or a mesh of conductive wires. A semiconductor substrate is attached to the transparent handle substrate employing an adhesive layer. The semiconductor substrate is thinned in the bonded structure to form a stack of the transparent handle substrate and the semiconductor interposer. The thinned bonded structure may be loaded into a processing chamber and electrostatically chucked employing the blanket conductive film or the mesh of conductive wires. The semiconductor interposer may be bonded to a semiconductor chip or a packaging substrate employing C4 bonding or intermetallic alloy bonding. Illumination of ultraviolet radiation to the adhesive layer is enabled, for example, by removal of the blanket conductive film or through the mesh so that the transparent handle substrate may be detached. The semiconductor interposer may then be bonded to a packaging substrate or a semiconductor chip.
摘要翻译： 电介质透明手柄基板的背面涂覆有橡皮布导电膜或导电丝网。 使用粘合剂层将半导体衬底附接到透明手柄衬底。 半导体衬底在接合结构中变薄以形成透明手柄衬底和半导体插入器的堆叠。 减薄的粘合结构可以被加载到处理室中并且使用橡皮布导电膜或导线的网状物静电夹持。 半导体插入件可以结合到采用C4键合或金属间化合物键合的半导体芯片或封装衬底。 照射紫外线到粘合剂层是可以实现的，例如，通过去除橡皮布传导膜或通过网格，使透明手柄基板可以分离。 然后可以将半导体中介层结合到封装衬底或半导体芯片。
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公开(公告)号：US20110227225A1
公开(公告)日：2011-09-22
申请号：US13116622
申请日：2011-05-26
申请人： Daniel C. Edelstein , Edward C. Cooney, III , John A. Fitzsimmons , Jeffrey P. Gambino , Anthony K. Stamper
发明人： Daniel C. Edelstein , Edward C. Cooney, III , John A. Fitzsimmons , Jeffrey P. Gambino , Anthony K. Stamper
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L23/5226 , H01L2924/0002 , Y10T428/12493 , H01L2924/00
摘要： Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.
摘要翻译： 通过在集成电路中的铜通孔/布线连接中形成铜合金，同时通过将合金限制在所述合金的界面区域来最小化合金的不利电效应来获得铜集成电路互连的改进的机械和粘合强度和断裂性 通孔/布线连接，而不在其他地方，通过减小或基本消除导电路径中合金的厚度。 通过所有可用的合金材料与铜，铜合金或其他金属及其合金的反应，合金位置和组成进一步稳定。
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