公开(公告)号：US20100148371A1

公开(公告)日：2010-06-17

申请号：US12334433

申请日：2008-12-12

申请人： Kenneth Kaskoun ,  Shiqun Gu ,  Bart Swinnen

发明人： Kenneth Kaskoun ,  Shiqun Gu ,  Bart Swinnen

IPC分类号： H01L21/50 ,  H01L23/538

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2224/06181 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are coupled together. The first set of vias are physically smaller than the second set of vias. The first set of vias are produced prior to circuitry on the die, and the second set of vias are produced after circuitry on the die. A second die having a set of interconnects is stacked relative to the first die in which the interconnects couple to the first set of vias.

摘要翻译： 多层IC器件包含第一裸片，其包括具有第一组和第二组通孔的衬底。 第一组通孔从衬底的一侧延伸，并且第二组通孔从衬底的相对侧延伸。 两组通孔耦合在一起。 第一组通孔在物理上小于第二组通孔。 第一组通孔在芯片上的电路之前产生，并且第二组通孔在芯片上的电路之后产生。 具有一组互连件的第二管芯相对于第一管芯堆叠，其中互连件耦合到第一组通孔。

公开(公告)号：US07553772B1

公开(公告)日：2009-06-30

申请号：US11046949

申请日：2005-01-31

申请人： Shiqun Gu ,  Wai Lo ,  Hong Lin

发明人： Shiqun Gu ,  Wai Lo ,  Hong Lin

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76814 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/3105 ,  H01L21/31662 ,  H01L21/3185

摘要： Process and apparatus provide reactive radicals generated from a remote plasma source which contact a portion of a substrate surface simultaneous with a contact of the same substrate surface with a light source which locally activates the portion of the substrate surface in contact with said radicals.

摘要翻译： 工艺和设备提供从远程等离子体源产生的反应性基团，其接触衬底表面的一部分，同时与同一衬底表面的接触与局部激活与所述自由基接触的衬底表面的部分的光源。

公开(公告)号：US20070004191A1

公开(公告)日：2007-01-04

申请号：US11298274

申请日：2005-12-08

申请人： Shiqun Gu ,  Peter McGrath ,  James Elmer ,  Richard Carter

发明人： Shiqun Gu ,  Peter McGrath ,  James Elmer ,  Richard Carter

IPC分类号： H01L21/4763

CPC分类号： H01L21/76838 ,  B82Y10/00 ,  H01L21/32136 ,  H01L21/32139 ,  H01L51/0018 ,  H01L51/0048 ,  Y10S977/742

摘要： A method for patterning CNTs on a wafer wherein a CNT layer is provided on a substrate, a hard mask film is deposited on the CNT layer, a BARC layer (optional) is coated on the hard mask film, and a resist is patterned on the BARC layer (or directly on the hard mask film if the BARC layer is not included). Then, the resist pattern is effectively transferred to the hard mask film by etching the BARC layer (if provided) and etching partly into, but not entirely through, the hard mask film (i.e., etching is stopped before reaching the CNT layer) Then, the resist and the BARC layer (if provided) is stripped, and the hard mask pattern is effectively transferred to the CNTs by etching away (preferably by using Cl, F plasma) the portions of the hard mask which have been already partially etched away.

摘要翻译： 一种用于在晶片上图案化CNT的方法，其中CNT层设置在基板上，硬掩模膜沉积在CNT层上，BARC层（可选）涂覆在硬掩模膜上，并且抗蚀剂在 BARC层（或直接在硬掩模膜上，如果不包括BARC层）。 然后，通过蚀刻BARC层（如果提供）并且部分地蚀刻到硬掩模膜上而不是完全通过硬掩模膜（即，在到达CNT层之前停止蚀刻），将抗蚀剂图案有效地转移到硬掩模膜。然后， 剥离抗蚀剂和BARC层（如果提供），并且通过蚀刻掉（优选通过使用Cl，F等离子体）已经部分蚀刻掉的硬掩模的部分，将硬掩模图案有效地转移到CNT。

公开(公告)号：US20060035455A1

公开(公告)日：2006-02-16

申请号：US10915719

申请日：2004-08-10

申请人： Wai Lo ,  Hong Lin ,  Shiqun Gu ,  Wilbur Catabay ,  Zhihai Wang ,  Wei-Jen Hsia

发明人： Wai Lo ,  Hong Lin ,  Shiqun Gu ,  Wilbur Catabay ,  Zhihai Wang ,  Wei-Jen Hsia

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.

公开(公告)号：US06972840B1

公开(公告)日：2005-12-06

申请号：US10680503

申请日：2003-10-06

申请人： Shiqun Gu ,  Peter Gerard McGrath ,  Ryan Tadashi Fujimoto

发明人： Shiqun Gu ,  Peter Gerard McGrath ,  Ryan Tadashi Fujimoto

IPC分类号： H01J37/32 ,  H01L21/00 ,  H01L23/544 ,  G01N21/00

CPC分类号： H01L22/34 ,  H01J37/32935 ,  H01J37/32972 ,  H01L21/67069 ,  H01L21/67253 ,  Y10T156/1734

摘要： Optical emission spectra from a test wafer during a plasma process are measured using a spectrometer. The plasma charging voltage retained by (detected by) the test wafer is measured after the process step is completed. The emission spectra are correlated with the plasma charging voltage to identify the species contributing to the plasma charging voltage. The optical emission spectra are monitored in real time to optimize the plasma process to prevent plasma charging damage. The optical emission spectra are also monitored to control the plasma process drift.

摘要翻译： 使用光谱仪测量等离子体处理期间来自测试晶片的光发射光谱。 在处理步骤完成之后测量由测试晶片（由检测到的）保持的等离子体充电电压。 发射光谱与等离子体充电电压相关，以识别有助于等离子体充电电压的物质。 实时监测光发射光谱，以优化等离子体处理以防止等离子体充电损坏。 还监测光发射光谱以控制等离子体工艺漂移。

公开(公告)号：US20050064716A1

公开(公告)日：2005-03-24

申请号：US10951646

申请日：2004-09-28

申请人： Hong Lin ,  Shiqun Gu ,  Wai Lo ,  James Elmer

发明人： Hong Lin ,  Shiqun Gu ,  Wai Lo ,  James Elmer

IPC分类号： H01L21/28 ,  H01L21/311 ,  H01L29/51 ,  H01L29/80 ,  H01L21/302 ,  H01L21/461 ,  H01L31/112

CPC分类号： H01L29/518 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/31111 ,  H01L29/51 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517

摘要： A method of forming a high k gate insulation layer in an integrated circuit on a substrate. A high k layer is deposited onto the substrate, and patterned with a mask to define the high k gate insulation layer and exposed portions of the high k layer. The exposed portions of the high k layer are subjected to an in-situ plasma species that causes structural damage to the exposed portions of the high k layer. The structurally damaged exposed portions of the high k layer are wet etched to leave the high k gate insulation layer.

摘要翻译： 在基板上的集成电路中形成高k栅极绝缘层的方法。 将高k层沉积在衬底上，并用掩模图案以限定高k栅极绝缘层和高k层的暴露部分。 高k层的暴露部分经受原位等离子体物质，这导致对高k层的暴露部分的结构损伤。 高k层的结构损坏的暴露部分被湿蚀刻以留下高k栅极绝缘层。

公开(公告)号：US06743669B1

公开(公告)日：2004-06-01

申请号：US10164227

申请日：2002-06-05

申请人： Hong Lin ,  Shiqun Gu ,  Peter McGrath

发明人： Hong Lin ,  Shiqun Gu ,  Peter McGrath

IPC分类号： H01L218234

CPC分类号： H01L21/823481 ,  H01L21/3144 ,  H01L21/3185 ,  H01L27/0629

摘要： A dielectric film block is used in semiconductor processing to protect selected areas of the wafer from silicidation. The selected areas may include resistors. A first layer of oxide is formed on the resistor and a second layer comprising SiON or Si3N4 is disposed on the oxide. A mask is patterned to allow etching to take place in the areas where silicide formation is desired. The oxide layer serves as an etch stop layer during etching of the second layer.

摘要翻译： 在半导体处理中使用介电膜块来保护晶片的选定区域免受硅化。 所选择的区域可以包括电阻器。 在电阻器上形成第一层氧化物，并且在氧化物上设置包含SiON或Si3N4的第二层。 对掩模进行图案化以允许在需要硅化物形成的区域进行蚀刻。 氧化物层在蚀刻第二层期间用作蚀刻停止层。

公开(公告)号：US5629953A

公开(公告)日：1997-05-13

申请号：US435353

申请日：1995-05-05

申请人： Stephen G. Bishop ,  Shiqun Gu ,  Douglas A. Turnbull

发明人： Stephen G. Bishop ,  Shiqun Gu ,  Douglas A. Turnbull

IPC分类号： H01S3/094 ,  H01S3/16 ,  H01S3/17 ,  H01S3/14

CPC分类号： H01S3/17 ,  H01S3/094 ,  H01S3/1608 ,  H01S3/1613

摘要： The present invention concerns an optical pumping system making use of a broad continuous absorption band in rare earth doped chalcogenide glasses. The absorption band is approximately 400 nm in width and extends from approximately 600 nm to 1000 nm. Through subjecting the glass to pumping light from an excitation source within the broad absorption band, photoluminescence emissions are produced. Size and strength of the pumping absorption band are such that great flexibility is provided in implementation of the excitation source. Specific embodiments of4 the present invention may utilize Er or Pr doped Ge.sub.33 As.sub.12 S.sub.55 or As.sub.2 S. Selection of the chalcogenide host may adjust the broad absorption band. As an example, a narrower gap chalcogenide glass, such as Ge.sub.28 Sb.sub.12 Se.sub.60, should extend the broad absorption band into the 1064 nm wavelength. Lasers, optical amplifiers and other devices may be realized in accordance with the pumping system of the present invention, and the chalcogenide glass may be formed as a thin film combined on a substrate with a semi-conductor laser.

摘要翻译： 本发明涉及一种利用稀土掺杂的硫族化物玻璃中的宽连续吸收带的光泵送系统。 吸收带的宽度约为400nm，从约600nm延伸至1000nm。 通过使玻璃从宽吸收带内的激发源泵浦光，产生光致发光。 泵浦吸收带的尺寸和强度使得在实现激发源时提供了很大的灵活性。 本发明的具体实施方案可以利用Er或Pr掺杂的Ge33As12S55或As2S。 选择硫属化物主体可以调节宽吸收带。 例如，较窄的间隙硫族化物玻璃，例如Ge28Sb12Se60，应将宽吸收带扩展到1064nm波长。 可以根据本发明的泵送系统来实现激光器，光放大器和其他装置，并且硫族化物玻璃可以形成为在半导体激光器的基板上组合的薄膜。

公开(公告)号：US09431298B2

公开(公告)日：2016-08-30

申请号：US12939439

申请日：2010-11-04

申请人： Daniel W. Perry ,  Shiqun Gu

发明人： Daniel W. Perry ,  Shiqun Gu

IPC分类号： H01L23/52 ,  H01L21/768 ,  G11C11/16 ,  G11C13/00 ,  G11C17/16 ,  H01L23/525

CPC分类号： H01L21/76898 ,  G11C11/16 ,  G11C13/0002 ,  G11C17/16 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit, a method for making an integrated circuit product, and methods for customizing an integrated circuit are disclosed. Integrated circuit elements including programmable elements, such as fuses, PROMs, RRAMs, MRAMs, or the like, are formed on the frontside of a substrate. Vias are formed through the substrate from its frontside to its backside to establish conduction paths to at least some of the programmable elements from the backside. A programming stimulus is applied to at least some of the vias from the backside to program at least some of the frontside programmable elements.

摘要翻译： 公开了集成电路，制造集成电路产品的方法以及用于定制集成电路的方法。 包括诸如保险丝，PROM，RRAM，MRAM等可编程元件的集成电路元件形成在衬底的前侧。 通孔从其前侧到其背面通过衬底形成，从背面建立至少一些可编程元件的传导路径。 编程刺激从后侧应用于至少一些通孔，以编程前端可编程元件中的至少一些。

公开(公告)号：US20140061744A1

公开(公告)日：2014-03-06

申请号：US13602714

申请日：2012-09-04

申请人： Ron Zhang ,  Lew G. Chua-Eoan ,  Shiqun Gu

发明人： Ron Zhang ,  Lew G. Chua-Eoan ,  Shiqun Gu

IPC分类号： H01L27/06 ,  H01L29/66

CPC分类号： H01L27/0629 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L27/13 ,  H01L28/86 ,  H01L29/66795

摘要： A capacitor includes a semiconductor substrate. The capacitor also includes a first terminal having a fin disposed on a surface of the semiconductor substrate. The capacitor further includes a dielectric layer disposed onto the fin. The capacitor still further includes a second terminal having a FinFET compatible high-K metal gate disposed proximate and adjacent to the fin.

摘要翻译： 电容器包括半导体衬底。 电容器还包括具有设置在半导体衬底的表面上的翅片的第一端子。 电容器还包括设置在鳍片上的电介质层。 电容器还包括具有FinFET兼容的高K金属栅极的第二端子，该金属栅极靠近并邻近鳍片。